i965: Add is_3src() to backend_instruction.
authorMatt Turner <mattst88@gmail.com>
Tue, 30 Dec 2014 03:29:21 +0000 (19:29 -0800)
committerMatt Turner <mattst88@gmail.com>
Sat, 24 Jan 2015 01:57:39 +0000 (17:57 -0800)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_shader.cpp
src/mesa/drivers/dri/i965/brw_shader.h
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

index cbdf976b6549f380886e66a2748604d0568420bc..be30d976c14fd6a5ab8a6b78c92d6c6e7a86813d 100644 (file)
@@ -677,6 +677,12 @@ backend_reg::is_accumulator() const
           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 }
 
+bool
+backend_instruction::is_3src() const
+{
+   return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
+}
+
 bool
 backend_instruction::is_tex() const
 {
index 54d770e1635b42e8d05bb51700f5c633f3e6802c..6fc86e1c549bf8af7edd1275651544c3e6678bff 100644 (file)
@@ -82,6 +82,7 @@ struct bblock_t;
 
 #ifdef __cplusplus
 struct backend_instruction : public exec_node {
+   bool is_3src() const;
    bool is_tex() const;
    bool is_math() const;
    bool is_control_flow() const;
index 9e47dd939902df38bb6a26f862b72df1393305c5..bf15941e10214beaeb28496d567e72670ccdec90 100644 (file)
@@ -308,11 +308,7 @@ try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
        inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
       return false;
 
-   bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
-                        inst->opcode == BRW_OPCODE_MAD ||
-                        inst->opcode == BRW_OPCODE_BFE ||
-                        inst->opcode == BRW_OPCODE_BFI2);
-   if (is_3src_inst && value.file == UNIFORM)
+   if (inst->is_3src() && value.file == UNIFORM)
       return false;
 
    if (inst->is_send_from_grf())