(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 8b7ca773ad00c1b8ac099ea79af84dae93827290..e69bf86bb6b46429d6c5d0d3a382526116a3279b 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -360,12 +360,20 @@ a cumulative series of overlapping add operations into the Execution units of
 the underlying hardware.
 
 Other examples include shift-mask operations where a Vector of inserts
-into a single destination register is required, as a way to construct
+into a single destination register is required (see [[sv/bitmanip]], bmset),
+as a way to construct
 a value quickly from multiple arbitrary bit-ranges and bit-offsets.
 Using the same register as both the source and destination, with Vectors
 of different offsets masks and values to be inserted has multiple
 applications including Video, cryptography and JIT compilation.
 
+    # assume VL=4:
+    # * Vector of shift-offsets contained in RC (r12.v)
+    # * Vector of masks contained in RB (r8.v)
+    # * Vector of values to be masked-in in RA (r4.v)
+    # * Scalar destination RT (r0) to receive all mask-offset values
+    sv.bmset/mr r0, r4.v, r8.v, r12.v
+
 Due to the Deterministic Scheduling,
 Subtract and Divide are still permitted to be executed in this mode,
 although from an algorithmic perspective it is strongly discouraged.