stop using MSR vfirst bit, move to SVSTATE bit 63 instead

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 8ad064cabf6bfde0cb38e9d5272a5b46cd289b8c..b825e4904884b98467ec8b1517a0327733d73a9e 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -32,7 +32,7 @@ Pseudo-code:
         SVSTATE[7:13] <- VL
         if _RT != 0b00000 then
            GPR(_RT) <- [0]*57 || VL
-        MSR[6] <- vf
+        SVSTATE[63] <- vf
 
 Special Registers Altered:
 
@@ -118,10 +118,10 @@ Pseudo-code:
         SVSHAPE1[28:29] <- 0b01           # j+halfstep schedule
         # FRC (coefficients)
         SVSHAPE2[28:29] <- 0b10           # k schedule
-    # set VL, MVL and MSR Vertical-First
+    # set VL, MVL and Vertical-First
     SVSTATE[0:6] <- vlen
     SVSTATE[7:13] <- vlen
-    MSR[6] <- vf
+    SVSTATE[63] <- vf
 
 Special Registers Altered:
 

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index 057bd262d80624f9dc950f41c3da98449600ba55..5c60bd972bfbf0e67967ada8fcf4b768e02049f8 100644 (file)
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -90,7 +90,6 @@ class MSRb:
     SF  = 0     # Sixty-Four bit mode
     HV  = 3     # Hypervisor state
     UND = 5     # Undefined behavior state (see Bk 2, Sect. 3.2.1)
-    SVF = 6     # SVP64 "Vertical First" mode
     TSs = 29    # Transactional State (subfield)
     TSe = 30    # Transactional State (subfield)
     TM  = 31    # Transactional Memory Available

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 5d5954b30601478d22ffd756076c258b03adae1d..caa0684de8188631399ab14193c397443a9ba926 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1450,7 +1450,7 @@ class ISACaller:
                 # reset at end of loop including exit Vertical Mode
                 log ("SVSTATE_NEXT: end of loop, reset")
                 self.svp64_reset_loop()
-                self.msr[MSRb.SVF] = 0
+                self.svstate.vfirst = 0
                 self.update_nia()
                 if rc_en:
                     results = [SelectableInt(0, 64)]
@@ -1477,7 +1477,7 @@ class ISACaller:
                     # reset at end of loop including exit Vertical Mode
                     log ("SVSTATE_NEXT: after increments, reset")
                     self.svp64_reset_loop()
-                    self.msr[MSRb.SVF] = 0
+                    self.svstate.vfirst = 0
 
         elif self.is_svp64_mode:
             yield from self.svstate_post_inc()
@@ -1587,8 +1587,9 @@ class ISACaller:
 
     def svstate_post_inc(self, vf=0):
         # check if SV "Vertical First" mode is enabled
-        log ("    SV Vertical First", vf, self.msr[MSRb.SVF].value)
-        if not vf and self.msr[MSRb.SVF].value == 1:
+        vfirst = self.svstate.vfirst
+        log ("    SV Vertical First", vf, vfirst)
+        if not vf and vfirst == 1:
             self.update_nia()
             return True
 

diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index 317e34222af8673739cf847e873b475f5809e926..a3f239b2b7cae4d9a50090c8a7a2f1c24f9847f6 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -43,14 +43,14 @@ class DecoderTestCase(FHDLTestCase):
             print ("        mvl", bin(sim.svstate.maxvl))
             print ("    srcstep", bin(sim.svstate.srcstep))
             print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate.vfirst))
             self.assertEqual(sim.svstate.vl, 10)
             self.assertEqual(sim.svstate.maxvl, 10)
             self.assertEqual(sim.svstate.srcstep, 2)
             self.assertEqual(sim.svstate.dststep, 2)
+            self.assertEqual(sim.svstate.vfirst, 1)
             print("      gpr1", sim.gpr(0))
             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
-            print("      msr", bin(sim.msr.value))
-            self.assertEqual(sim.msr, SelectableInt(1<<(63-6), 64))
 
     def test__svstep_2(self):
         """tests svstep when it reaches VL
@@ -74,15 +74,15 @@ class DecoderTestCase(FHDLTestCase):
             print ("        mvl", bin(sim.svstate.maxvl))
             print ("    srcstep", bin(sim.svstate.srcstep))
             print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate.vfirst))
             self.assertEqual(sim.svstate.vl, 2)
             self.assertEqual(sim.svstate.maxvl, 2)
             self.assertEqual(sim.svstate.srcstep, 0)
             self.assertEqual(sim.svstate.dststep, 0)
+            # when end reached, vertical mode is exited
+            self.assertEqual(sim.svstate.vfirst, 0)
             print("      gpr1", sim.gpr(0))
             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
-            # when end reached, vertical mode is exited
-            print("      msr", bin(sim.msr.value))
-            self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64))
             CR0 = sim.crl[0]
             print("      CR0", bin(CR0.get_range().value))
             self.assertEqual(CR0[CRFields.EQ], 1)
@@ -112,6 +112,7 @@ class DecoderTestCase(FHDLTestCase):
             print ("        mvl", bin(sim.svstate.maxvl))
             print ("    srcstep", bin(sim.svstate.srcstep))
             print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate. vfirst))
             self.assertEqual(sim.svstate.vl, 3)
             self.assertEqual(sim.svstate.maxvl, 3)
             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
@@ -119,8 +120,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.svstate.dststep, 2)
             print("      gpr1", sim.gpr(0))
             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
-            print("      msr", bin(sim.msr.value))
-            self.assertEqual(sim.msr, SelectableInt(1<<(63-6), 64))
+            self.assertEqual(sim.svstate.vfirst, 1)
             CR0 = sim.crl[0]
             print("      CR0", bin(CR0.get_range().value))
             self.assertEqual(CR0[CRFields.EQ], 0)
@@ -233,13 +233,13 @@ class DecoderTestCase(FHDLTestCase):
             print ("        mvl", bin(sim.svstate.maxvl))
             print ("    srcstep", bin(sim.svstate.srcstep))
             print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate. vfirst))
             self.assertEqual(sim.svstate.vl, 2)
             self.assertEqual(sim.svstate.maxvl, 2)
             self.assertEqual(sim.svstate.srcstep, 0)
             self.assertEqual(sim.svstate.dststep, 0)
             # when end reached, vertical mode is exited
-            print("      msr", bin(sim.msr.value))
-            self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64))
+            self.assertEqual(sim.svstate.vfirst, 0)
             CR0 = sim.crl[0]
             print("      CR0", bin(CR0.get_range().value))
             self.assertEqual(CR0[CRFields.EQ], 1)
@@ -311,13 +311,13 @@ class DecoderTestCase(FHDLTestCase):
             print ("        mvl", bin(sim.svstate.maxvl))
             print ("    srcstep", bin(sim.svstate.srcstep))
             print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate. vfirst))
             self.assertEqual(sim.svstate.vl, 2)
             self.assertEqual(sim.svstate.maxvl, 2)
             self.assertEqual(sim.svstate.srcstep, 0)
             self.assertEqual(sim.svstate.dststep, 0)
             # when end reached, vertical mode is exited
-            print("      msr", bin(sim.msr.value))
-            self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64))
+            self.assertEqual(sim.svstate.vfirst, 0)
             CR0 = sim.crl[0]
             print("      CR0", bin(CR0.get_range().value))
             self.assertEqual(CR0[CRFields.EQ], 1)