#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
mips_multipass_dfa_lookahead
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS \
+ (TARGET_DEFAULT \
+ | TARGET_CPU_DEFAULT \
+ | TARGET_ENDIAN_DEFAULT \
+ | TARGET_FP_EXCEPTIONS_DEFAULT \
+ | MASK_CHECK_ZERO_DIV \
+ | MASK_FUSED_MADD)
+
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
if ((target_flags_explicit & MASK_LONG64) == 0)
{
+ if (TARGET_INT64)
+ target_flags |= MASK_LONG64;
/* If no type size setting options (-mlong64,-mint64,-mlong32)
were used, then set the type sizes. In the EABI in 64 bit mode,
longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
ABI. */
- if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
+ else if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
target_flags |= MASK_LONG64;
else
target_flags &= ~MASK_LONG64;
if (TARGET_INT64)
warning ("-mint64 is a deprecated option");
+ if (TARGET_INT64 && !TARGET_LONG64)
+ error ("unsupported combination: %s", "-mint64 -mlong32");
+
if (mips_fix_vr4130_string && mips_fix_vr4130_string[0] != 0)
error ("unrecognized option %<-mfix-vr4130%s%>", mips_fix_vr4130_string);
/* Make sure that the user didn't turn off paired single support when
MIPS-3D support is requested. */
- if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE)
+ if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
&& !TARGET_PAIRED_SINGLE_FLOAT)
error ("-mips3d requires -mpaired-single");
- /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE. */
+ /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
if (TARGET_MIPS3D)
- target_flags |= MASK_PAIRED_SINGLE;
+ target_flags |= MASK_PAIRED_SINGLE_FLOAT;
/* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
and TARGET_HARD_FLOAT are both true. */
/* Define all the builtins related to c.cond.fmt condition COND. */
#define CMP_BUILTINS(COND) \
- MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE), \
+ MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
- CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE), \
+ CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
CMP_4S_BUILTINS (c, COND), \
CMP_4S_BUILTINS (cabs, COND)
static const struct builtin_description mips_bdesc[] =
{
- DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
- DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
- DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
- DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
- DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE),
- DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
- DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
- DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
-
- DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, MASK_PAIRED_SINGLE),
+ DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+
+ DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
+ MASK_PAIRED_SINGLE_FLOAT),
DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
static const struct builtin_description sb1_bdesc[] =
{
- DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE)
+ DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
};
/* This helps provide a mapping from builtin function codes to bdesc
Boston, MA 02111-1307, USA. */
-/* Standard GCC variables that we reference. */
-
-extern int target_flags;
-
/* MIPS external variables defined in mips.c. */
/* Which processor to schedule for. Since there is no difference between
extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
-extern const char *mips_fix_vr4130_string;
extern const struct mips_cpu_info mips_cpu_info_table[];
extern const struct mips_cpu_info *mips_arch_info;
extern const struct mips_cpu_info *mips_tune_info;
\f
/* Run-time compilation parameters selecting different hardware subsets. */
-/* Macros used in the machine description to test the flags. */
-
- /* Bits for real switches */
-#define MASK_INT64 0x00000001 /* ints are 64 bits */
-#define MASK_LONG64 0x00000002 /* longs are 64 bits */
-#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
-#define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
- multiply-add operations. */
-#define MASK_EXPLICIT_RELOCS 0x00000010 /* Use relocation operators. */
-#define MASK_MEMCPY 0x00000020 /* call memcpy instead of inline code*/
-#define MASK_SOFT_FLOAT 0x00000040 /* software floating point */
-#define MASK_FLOAT64 0x00000080 /* fp registers are 64 bits */
-#define MASK_ABICALLS 0x00000100 /* emit .abicalls/.cprestore/.cpload */
-#define MASK_XGOT 0x00000200 /* emit big-got PIC */
-#define MASK_LONG_CALLS 0x00000400 /* Always call through a register */
-#define MASK_64BIT 0x00000800 /* Use 64 bit GP registers and insns */
-#define MASK_EMBEDDED_DATA 0x00001000 /* Reduce RAM usage, not fast code */
-#define MASK_BIG_ENDIAN 0x00002000 /* Generate big endian code */
-#define MASK_SINGLE_FLOAT 0x00004000 /* Only single precision FPU. */
-#define MASK_MAD 0x00008000 /* Generate mad/madu as on 4650. */
-#define MASK_4300_MUL_FIX 0x00010000 /* Work-around early Vr4300 CPU bug */
-#define MASK_MIPS16 0x00020000 /* Generate mips16 code */
-#define MASK_NO_CHECK_ZERO_DIV \
- 0x00040000 /* divide by zero checking */
-#define MASK_BRANCHLIKELY 0x00080000 /* Generate Branch Likely
- instructions. */
-#define MASK_UNINIT_CONST_IN_RODATA \
- 0x00100000 /* Store uninitialized
- consts in rodata */
-#define MASK_FIX_R4000 0x00200000 /* Work around R4000 errata. */
-#define MASK_FIX_R4400 0x00400000 /* Work around R4400 errata. */
-#define MASK_FIX_SB1 0x00800000 /* Work around SB-1 errata. */
-#define MASK_FIX_VR4120 0x01000000 /* Work around VR4120 errata. */
-#define MASK_VR4130_ALIGN 0x02000000 /* Perform VR4130 alignment opts. */
-#define MASK_FP_EXCEPTIONS 0x04000000 /* FP exceptions are enabled. */
-#define MASK_DIVIDE_BREAKS 0x08000000 /* Divide by zero check uses
- break instead of trap. */
-#define MASK_PAIRED_SINGLE 0x10000000 /* Support paired-single FPU. */
-#define MASK_MIPS3D 0x20000000 /* Support MIPS-3D instructions. */
-#define MASK_SYM32 0x40000000 /* Assume 32-bit symbol values. */
-
- /* Debug switches, not documented */
-#define MASK_DEBUG 0 /* unused */
-#define MASK_DEBUG_D 0 /* don't do define_split's */
-
- /* Dummy switches used only in specs */
-#define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
-
- /* r4000 64 bit sizes */
-#define TARGET_INT64 ((target_flags & MASK_INT64) != 0)
-#define TARGET_LONG64 ((target_flags & MASK_LONG64) != 0)
-#define TARGET_FLOAT64 ((target_flags & MASK_FLOAT64) != 0)
-#define TARGET_64BIT ((target_flags & MASK_64BIT) != 0)
-
- /* Mips vs. GNU linker */
-#define TARGET_SPLIT_ADDRESSES ((target_flags & MASK_SPLIT_ADDR) != 0)
-
- /* Debug Modes */
-#define TARGET_DEBUG_MODE ((target_flags & MASK_DEBUG) != 0)
-#define TARGET_DEBUG_D_MODE ((target_flags & MASK_DEBUG_D) != 0)
-
- /* call memcpy instead of inline code */
-#define TARGET_MEMCPY ((target_flags & MASK_MEMCPY) != 0)
-
- /* .abicalls, etc from Pyramid V.4 */
-#define TARGET_ABICALLS ((target_flags & MASK_ABICALLS) != 0)
-#define TARGET_XGOT ((target_flags & MASK_XGOT) != 0)
-
- /* software floating point */
-#define TARGET_SOFT_FLOAT ((target_flags & MASK_SOFT_FLOAT) != 0)
-#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
-
- /* always call through a register */
-#define TARGET_LONG_CALLS ((target_flags & MASK_LONG_CALLS) != 0)
-
- /* for embedded systems, optimize for
- reduced RAM space instead of for
- fastest code. */
-#define TARGET_EMBEDDED_DATA ((target_flags & MASK_EMBEDDED_DATA) != 0)
-
- /* always store uninitialized const
- variables in rodata, requires
- TARGET_EMBEDDED_DATA. */
-#define TARGET_UNINIT_CONST_IN_RODATA \
- ((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)
-
- /* generate big endian code. */
-#define TARGET_BIG_ENDIAN ((target_flags & MASK_BIG_ENDIAN) != 0)
-
-#define TARGET_SINGLE_FLOAT ((target_flags & MASK_SINGLE_FLOAT) != 0)
-#define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
-
-#define TARGET_MAD ((target_flags & MASK_MAD) != 0)
-
-#define TARGET_FUSED_MADD ((target_flags & MASK_NO_FUSED_MADD) == 0)
-
-#define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
-
-#define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
-#define TARGET_DIVIDE_TRAPS ((target_flags & MASK_DIVIDE_BREAKS) == 0)
-
-#define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
-
-#define TARGET_FIX_SB1 ((target_flags & MASK_FIX_SB1) != 0)
-
- /* Work around R4000 errata. */
-#define TARGET_FIX_R4000 ((target_flags & MASK_FIX_R4000) != 0)
-
- /* Work around R4400 errata. */
-#define TARGET_FIX_R4400 ((target_flags & MASK_FIX_R4400) != 0)
-#define TARGET_FIX_VR4120 ((target_flags & MASK_FIX_VR4120) != 0)
-#define TARGET_FIX_VR4130 (mips_fix_vr4130_string != 0)
-#define TARGET_VR4130_ALIGN ((target_flags & MASK_VR4130_ALIGN) != 0)
-
-#define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
-
-#define TARGET_PAIRED_SINGLE_FLOAT \
- ((target_flags & MASK_PAIRED_SINGLE) != 0)
-#define TARGET_MIPS3D ((target_flags & MASK_MIPS3D) != 0)
-#define TARGET_SYM32 ((target_flags & MASK_SYM32) != 0)
-
-/* True if we should use NewABI-style relocation operators for
- symbolic addresses. This is never true for mips16 code,
- which has its own conventions. */
-
-#define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
-
-
/* True if the call patterns should be split into a jalr followed by
an instruction to restore $gp. This is only ever true for SVR4 PIC,
in which $gp is call-clobbered. It is only safe to split the load
\
} while (0)
-
-
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
-{ \
- SUBTARGET_TARGET_SWITCHES \
- {"int64", MASK_INT64 | MASK_LONG64, \
- N_("Use 64-bit int type")}, \
- {"long64", MASK_LONG64, \
- N_("Use 64-bit long type")}, \
- {"long32", -(MASK_LONG64 | MASK_INT64), \
- N_("Use 32-bit long type")}, \
- {"split-addresses", MASK_SPLIT_ADDR, \
- N_("Optimize lui/addiu address loads")}, \
- {"no-split-addresses", -MASK_SPLIT_ADDR, \
- N_("Don't optimize lui/addiu address loads")}, \
- {"gas", 0, \
- N_("Use GNU as (now ignored)")}, \
- {"gpOPT", 0, \
- N_("Use GP relative sdata/sbss sections (now ignored)")}, \
- {"gpopt", 0, \
- N_("Use GP relative sdata/sbss sections (now ignored)")}, \
- {"no-gpOPT", 0, \
- N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
- {"no-gpopt", 0, \
- N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
- {"stats", 0, \
- N_("Output compiler statistics (now ignored)")}, \
- {"no-stats", 0, \
- N_("Don't output compiler statistics")}, \
- {"memcpy", MASK_MEMCPY, \
- N_("Don't optimize block moves")}, \
- {"no-memcpy", -MASK_MEMCPY, \
- N_("Optimize block moves")}, \
- {"mips-tfile", MASK_MIPS_TFILE, \
- N_("Use mips-tfile asm postpass")}, \
- {"no-mips-tfile", -MASK_MIPS_TFILE, \
- N_("Don't use mips-tfile asm postpass")}, \
- {"soft-float", MASK_SOFT_FLOAT, \
- N_("Use software floating point")}, \
- {"hard-float", -MASK_SOFT_FLOAT, \
- N_("Use hardware floating point")}, \
- {"fp64", MASK_FLOAT64, \
- N_("Use 64-bit FP registers")}, \
- {"fp32", -MASK_FLOAT64, \
- N_("Use 32-bit FP registers")}, \
- {"gp64", MASK_64BIT, \
- N_("Use 64-bit general registers")}, \
- {"gp32", -MASK_64BIT, \
- N_("Use 32-bit general registers")}, \
- {"abicalls", MASK_ABICALLS, \
- N_("Use Irix PIC")}, \
- {"no-abicalls", -MASK_ABICALLS, \
- N_("Don't use Irix PIC")}, \
- {"long-calls", MASK_LONG_CALLS, \
- N_("Use indirect calls")}, \
- {"no-long-calls", -MASK_LONG_CALLS, \
- N_("Don't use indirect calls")}, \
- {"embedded-data", MASK_EMBEDDED_DATA, \
- N_("Use ROM instead of RAM")}, \
- {"no-embedded-data", -MASK_EMBEDDED_DATA, \
- N_("Don't use ROM instead of RAM")}, \
- {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
- N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
- {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
- N_("Don't put uninitialized constants in ROM")}, \
- {"eb", MASK_BIG_ENDIAN, \
- N_("Use big-endian byte order")}, \
- {"el", -MASK_BIG_ENDIAN, \
- N_("Use little-endian byte order")}, \
- {"single-float", MASK_SINGLE_FLOAT, \
- N_("Use single (32-bit) FP only")}, \
- {"double-float", -MASK_SINGLE_FLOAT, \
- N_("Don't use single (32-bit) FP only")}, \
- {"paired-single", MASK_PAIRED_SINGLE, \
- N_("Use paired-single floating point instructions")}, \
- {"no-paired-single", -MASK_PAIRED_SINGLE, \
- N_("Use paired-single floating point instructions")}, \
- {"ips3d", MASK_MIPS3D, \
- N_("Use MIPS-3D instructions")}, \
- {"no-mips3d", -MASK_MIPS3D, \
- N_("Use MIPS-3D instructions")}, \
- {"mad", MASK_MAD, \
- N_("Use multiply accumulate")}, \
- {"no-mad", -MASK_MAD, \
- N_("Don't use multiply accumulate")}, \
- {"no-fused-madd", MASK_NO_FUSED_MADD, \
- N_("Don't generate fused multiply/add instructions")}, \
- {"fused-madd", -MASK_NO_FUSED_MADD, \
- N_("Generate fused multiply/add instructions")}, \
- {"vr4130-align", MASK_VR4130_ALIGN, \
- N_("Perform VR4130-specific alignment optimizations")}, \
- {"no-vr4130-align", -MASK_VR4130_ALIGN, \
- N_("Don't perform VR4130-specific alignment optimizations")}, \
- {"fix4300", MASK_4300_MUL_FIX, \
- N_("Work around early 4300 hardware bug")}, \
- {"no-fix4300", -MASK_4300_MUL_FIX, \
- N_("Don't work around early 4300 hardware bug")}, \
- {"fix-sb1", MASK_FIX_SB1, \
- N_("Work around errata for early SB-1 revision 2 cores")}, \
- {"no-fix-sb1", -MASK_FIX_SB1, \
- N_("Don't work around errata for early SB-1 revision 2 cores")}, \
- {"fix-r4000", MASK_FIX_R4000, \
- N_("Work around R4000 errata")}, \
- {"no-fix-r4000", -MASK_FIX_R4000, \
- N_("Don't work around R4000 errata")}, \
- {"fix-r4400", MASK_FIX_R4400, \
- N_("Work around R4400 errata")}, \
- {"no-fix-r4400", -MASK_FIX_R4400, \
- N_("Don't work around R4400 errata")}, \
- {"fix-vr4120", MASK_FIX_VR4120, \
- N_("Work around certain VR4120 errata")}, \
- {"no-fix-vr4120", -MASK_FIX_VR4120, \
- N_("Don't work around certain VR4120 errata")}, \
- {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
- N_("Trap on integer divide by zero")}, \
- {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
- N_("Don't trap on integer divide by zero")}, \
- {"divide-traps", -MASK_DIVIDE_BREAKS, \
- N_("Use trap to check for integer divide by zero")}, \
- {"divide-breaks", MASK_DIVIDE_BREAKS, \
- N_("Use break to check for integer divide by zero")}, \
- { "branch-likely", MASK_BRANCHLIKELY, \
- N_("Use Branch Likely instructions, overriding default for arch")}, \
- { "no-branch-likely", -MASK_BRANCHLIKELY, \
- N_("Don't use Branch Likely instructions, overriding default for arch")}, \
- {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
- N_("Use NewABI-style %reloc() assembly operators")}, \
- {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
- N_("Use assembler macros instead of relocation operators")}, \
- {"ips16", MASK_MIPS16, \
- N_("Generate mips16 code") }, \
- {"no-mips16", -MASK_MIPS16, \
- N_("Generate normal-mode code") }, \
- {"xgot", MASK_XGOT, \
- N_("Lift restrictions on GOT size") }, \
- {"no-xgot", -MASK_XGOT, \
- N_("Do not lift restrictions on GOT size") }, \
- {"fp-exceptions", MASK_FP_EXCEPTIONS, \
- N_("FP exceptions are enabled") }, \
- {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
- N_("FP exceptions are not enabled") }, \
- {"sym32", MASK_SYM32, \
- N_("Assume all symbols have 32-bit values") }, \
- {"no-sym32", -MASK_SYM32, \
- N_("Don't assume all symbols have 32-bit values") }, \
- {"debug", MASK_DEBUG, \
- NULL}, \
- {"debugd", MASK_DEBUG_D, \
- NULL}, \
- {"", (TARGET_DEFAULT \
- | TARGET_CPU_DEFAULT \
- | TARGET_ENDIAN_DEFAULT \
- | TARGET_FP_EXCEPTIONS_DEFAULT), \
- NULL}, \
-}
-
/* Default target_flags if no switches are specified */
#ifndef TARGET_DEFAULT
N_("Don't call any cache flush functions"), 0}, \
{ "flush-func=", &mips_cache_flush_func, \
N_("Specify cache flush function"), 0}, \
- { "fix-vr4130", &mips_fix_vr4130_string, \
- N_("Work around VR4130 mflo/mfhi errata"), 0}, \
}
/* This is meant to be redefined in the host dependent files. */
#endif
\f
-#define SUBTARGET_TARGET_SWITCHES
-
#ifndef MIPS_ABI_DEFAULT
#define MIPS_ABI_DEFAULT ABI_32
#endif
--- /dev/null
+mabicalls
+Target Report Mask(ABICALLS)
+Use SVR4-style PIC
+
+mad
+Target Report Var(TARGET_MAD)
+Use PMC-style 'mad' instructions
+
+mbranch-likely
+Target Report Mask(BRANCHLIKELY)
+Use Branch Likely instructions, overriding the architecture default
+
+mcheck-zero-division
+Target Report Mask(CHECK_ZERO_DIV)
+Trap on integer divide by zero
+
+mdivide-breaks
+Target Report Mask(DIVIDE_BREAKS)
+Use branch-and-break sequences to check for integer divide by zero
+
+mdivide-traps
+Target Report InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
+Use trap instructions to check for integer divide by zero
+
+mdouble-float
+Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
+Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations
+
+mdebug
+Target Var(TARGET_DEBUG_MODE) Undocumented
+
+mdebugd
+Target Var(TARGET_DEBUG_D_MODE) Undocumented
+
+meb
+Target Report RejectNegative Mask(BIG_ENDIAN)
+Use big-endian byte order
+
+mel
+Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
+Use little-endian byte order
+
+membedded-data
+Target Report Var(TARGET_EMBEDDED_DATA)
+Use ROM instead of RAM
+
+mexplicit-relocs
+Target Report Mask(EXPLICIT_RELOCS)
+Use NewABI-style %reloc() assembly operators
+
+mfix-r4000
+Target Report Mask(FIX_R4000)
+Work around certain R4000 errata
+
+mfix-r4400
+Target Report Mask(FIX_R4400)
+Work around certain R4400 errata
+
+mfix-sb1
+Target Report Var(TARGET_FIX_SB1)
+Work around errata for early SB-1 revision 2 cores
+
+mfix-vr4120
+Target Report Var(TARGET_FIX_VR4120)
+Work around certain VR4120 errata
+
+mfix-vr4130
+Target Report Var(TARGET_FIX_VR4130)
+Work around VR4130 mflo/mfhi errata
+
+mfix4300
+Target Report Var(TARGET_4300_MUL_FIX)
+Work around an early 4300 hardware bug
+
+mfp-exceptions
+Target Report Mask(FP_EXCEPTIONS)
+FP exceptions are enabled
+
+mfp32
+Target Report RejectNegative InverseMask(FLOAT64)
+Use 32-bit floating-point registers
+
+mfp64
+Target Report RejectNegative Mask(FLOAT64)
+Use 64-bit floating-point registers
+
+mfused-madd
+Target Report Mask(FUSED_MADD)
+Generate floating-point multiply-add instructions
+
+mgp32
+Target Report RejectNegative InverseMask(64BIT)
+Use 32-bit general registers
+
+mgp64
+Target Report RejectNegative Mask(64BIT)
+Use 64-bit general registers
+
+mhard-float
+Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
+Allow the use of hardware floating-point instructions
+
+mint64
+Target Report RejectNegative Mask(INT64)
+Use a 64-bit int type
+
+mips16
+Target Report RejectNegative Mask(MIPS16)
+Generate mips16 code
+
+mips3d
+Target Report RejectNegative Mask(MIPS3D)
+Use MIPS-3D instructions
+
+mlong-calls
+Target Report Var(TARGET_LONG_CALLS)
+Use indirect calls
+
+mlong32
+Target Report RejectNegative InverseMask(LONG64, LONG32)
+Use a 32-bit long type
+
+mlong64
+Target Report RejectNegative Mask(LONG64)
+Use a 64-bit long type
+
+mmemcpy
+Target Report Var(TARGET_MEMCPY)
+Don't optimize block moves
+
+mmips-tfile
+Target
+Use the mips-tfile postpass
+
+mno-mips16
+Target Report RejectNegative InverseMask(MIPS16)
+Generate normal-mode code
+
+mno-mips3d
+Target Report RejectNegative InverseMask(MIPS3D)
+Do not use MIPS-3D instructions
+
+mpaired-single
+Target Report Mask(PAIRED_SINGLE_FLOAT)
+Use paired-single floating-point instructions
+
+msingle-float
+Target Report RejectNegative Mask(SINGLE_FLOAT)
+Restrict the use of hardware floating-point instructions to 32-bit operations
+
+msoft-float
+Target Report RejectNegative Mask(SOFT_FLOAT)
+Prevent the use of all hardware floating-point instructions
+
+msplit-addresses
+Target Report Mask(SPLIT_ADDRESSES)
+Optimize lui/addiu address loads
+
+msym32
+Target Report Var(TARGET_SYM32)
+Assume all symbols have 32-bit values
+
+muninit-const-in-rodata
+Target Report Var(TARGET_UNINIT_CONST_IN_RODATA)
+Put uninitialized constants in ROM (needs -membedded-data)
+
+mvr4130-align
+Target Report Mask(VR4130_ALIGN)
+Perform VR4130-specific alignment optimizations
+
+mxgot
+Target Report Var(TARGET_XGOT)
+Lift restrictions on GOT size
projects / gcc.git / commitdiff