[opcodes, sim, xcc] made *w insns illegal in RV32

now generic variants behave differently in RV32 and RV64.

diff --git a/riscv/decode.h b/riscv/decode.h
index 5348ccc101137b27694c6a0240043f6d1f629c26..fff6e0ea41eb5421bb3dc9e0e5294353f4273e44 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -6,19 +6,6 @@
 
 #include "config.h"
 
-#ifdef RISCV_ENABLE_64BIT
-# define support_64bit 1
-#else
-# define support_64bit 0
-#endif
-
-#ifdef RISCV_ENABLE_FPU
-# define support_fp 1
-#else
-# define support_fp 0
-#endif
-
-
 typedef int int128_t __attribute__((mode(TI)));
 typedef unsigned int uint128_t __attribute__((mode(TI)));
 
@@ -28,9 +15,8 @@ typedef uint64_t freg_t;
 
 const int OPCODE_BITS = 7;
 
-const int GPR_BITS = 8*sizeof(reg_t);
-const int GPRID_BITS = 5;
-const int NGPR = 1 << GPRID_BITS;
+const int XPRID_BITS = 5;
+const int NXPR = 1 << XPRID_BITS;
 
 const int FPR_BITS = 64;
 const int FPRID_BITS = 5;
@@ -87,8 +73,8 @@ struct itype_t
   unsigned opcode : OPCODE_BITS;
   unsigned funct : FUNCT_BITS;
   signed imm12 : IMM_BITS;
-  unsigned rs1 : GPRID_BITS;
-  unsigned rd : GPRID_BITS;
+  unsigned rs1 : XPRID_BITS;
+  unsigned rd : XPRID_BITS;
 };
 
 struct btype_t
@@ -96,8 +82,8 @@ struct btype_t
   unsigned opcode : OPCODE_BITS;
   unsigned funct : FUNCT_BITS;
   unsigned immlo : IMMLO_BITS;
-  unsigned rs2 : GPRID_BITS;
-  unsigned rs1 : GPRID_BITS;
+  unsigned rs2 : XPRID_BITS;
+  unsigned rs1 : XPRID_BITS;
   signed immhi : IMM_BITS-IMMLO_BITS;
 };
 
@@ -112,16 +98,16 @@ struct rtype_t
   unsigned opcode : OPCODE_BITS;
   unsigned funct : FUNCT_BITS;
   unsigned functr : FUNCTR_BITS;
-  unsigned rs2 : GPRID_BITS;
-  unsigned rs1 : GPRID_BITS;
-  unsigned rd : GPRID_BITS;
+  unsigned rs2 : XPRID_BITS;
+  unsigned rs1 : XPRID_BITS;
+  unsigned rd : XPRID_BITS;
 };
 
 struct ltype_t
 {
   unsigned opcode : OPCODE_BITS;
   unsigned bigimm : BIGIMM_BITS;
-  unsigned rd : GPRID_BITS;
+  unsigned rd : XPRID_BITS;
 };
 
 struct ftype_t
@@ -170,14 +156,14 @@ private:
 #endif
 
 // helpful macros, etc
-#define RS1 R[insn.rtype.rs1]
-#define RS2 R[insn.rtype.rs2]
-#define RD do_writeback(R,insn.rtype.rd)
-#define RA do_writeback(R,1)
-#define FRS1 FR[insn.ftype.rs1]
-#define FRS2 FR[insn.ftype.rs2]
-#define FRS3 FR[insn.ftype.rs3]
-#define FRD FR[insn.ftype.rd]
+#define RS1 XPR[insn.rtype.rs1]
+#define RS2 XPR[insn.rtype.rs2]
+#define RD do_writeback(XPR,insn.rtype.rd)
+#define RA do_writeback(XPR,1)
+#define FRS1 FPR[insn.ftype.rs1]
+#define FRS2 FPR[insn.ftype.rs2]
+#define FRS3 FPR[insn.ftype.rs3]
+#define FRD FPR[insn.ftype.rd]
 #define BIGIMM insn.ltype.bigimm
 #define SIMM insn.itype.imm12
 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
@@ -190,9 +176,10 @@ private:
             ((fsr & FSR_RD) >> FSR_RD_SHIFT))
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
-#define require64 if(gprlen != 64) throw trap_illegal_instruction
+#define xpr64 (xprlen == 64)
+#define require_xpr64 if(!xpr64) throw trap_illegal_instruction
 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
-#define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
+#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 #define set_fp_exceptions ({ set_fsr(fsr | \
                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
                              softfloat_exceptionFlags = 0; })
@@ -202,4 +189,6 @@ static inline sreg_t sext32(int32_t arg)
   return arg;
 }
 
+#define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
+
 #endif

diff --git a/riscv/execute.h b/riscv/execute.h
index ddc7b4271b094b1e03ab8eeb90bc591c36b98577..b8e396ad7312c4ca9be12d5fcb2ce5918de86433 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -768,11 +768,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/divuw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0xcf7)
-        {
-          #include "insns/mulhuw.h"
-          break;
-        }
         if((insn.bits & 0x1ffff) == 0xf7)
         {
           #include "insns/mulw.h"
@@ -783,11 +778,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/remw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x8f7)
-        {
-          #include "insns/mulhw.h"
-          break;
-        }
         if((insn.bits & 0x1ffff) == 0x10f7)
         {
           #include "insns/divw.h"

diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index a7ec78d0986aebbdb22406dd29421c556aebfd13..34d49ff31b932d4f48904e08336e2745ea8560e5 100644 (file)
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1 @@
-require64;
-RD = RS1 + RS2;
+RD = sext_xprlen(RS1 + RS2);

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index 2b9bae3a046ed5d1209499d1f8cd9e6b576b1dfd..88881e5aec6561853fed1c45fec349deae6a6e57 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1,2 +1 @@
-require64;
-RD = SIMM + RS1;
+RD = sext_xprlen(RS1 + SIMM);

diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index cf97d342432921a6341bd88547d8c8aecad000e0..23ae2788407d8721196b69b284e845a62f04ef0d 100644 (file)
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1 +1,2 @@
+require_xpr64;
 RD = sext32(SIMM + RS1);

diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
index f8715e36c46ffcc90de48217ed358ffa67e14561..4e2ed561677827fb72ffe7753d2d16823b88f017 100644 (file)
--- a/riscv/insns/addw.h
+++ b/riscv/insns/addw.h
@@ -1,2 +1,2 @@
+require_xpr64;
 RD = sext32(RS1 + RS2);
-

diff --git a/riscv/insns/amo_add.h b/riscv/insns/amo_add.h
index 3b59ffd7a609e77073499e05a01c1c46cb33fe2a..b8450bfd5038a76e7f1c762ebfa8b7f9bd08d1d5 100644 (file)
--- a/riscv/insns/amo_add.h
+++ b/riscv/insns/amo_add.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 + v);
 RD = v;

diff --git a/riscv/insns/amo_and.h b/riscv/insns/amo_and.h
index 729550194e0ad85ee45f29781e0eb166625c5e62..586eb7fb9683ebfa6b78874de10a923e5ec936bb 100644 (file)
--- a/riscv/insns/amo_and.h
+++ b/riscv/insns/amo_and.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 & v);
 RD = v;

diff --git a/riscv/insns/amo_max.h b/riscv/insns/amo_max.h
index f67f1a3038e4bdaf9ba102dd854e07b83b882349..1a0bc8afbcc733dbe2ce6542b921e148d11212f1 100644 (file)
--- a/riscv/insns/amo_max.h
+++ b/riscv/insns/amo_max.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 sreg_t v = mmu.load_int64(RS1);
 mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
 RD = v;

diff --git a/riscv/insns/amo_maxu.h b/riscv/insns/amo_maxu.h
index 9a3d9f62f16c8faca26f505dcffba3d0d09f10f4..ccfaf1dd1e5c7594d8e7e9f259da0c5e186d400f 100644 (file)
--- a/riscv/insns/amo_maxu.h
+++ b/riscv/insns/amo_maxu.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, std::max(RS2,v));
 RD = v;

diff --git a/riscv/insns/amo_min.h b/riscv/insns/amo_min.h
index 4acfe74065219e8404d7f1cfe981a23ddb30f6b1..4f3b6d6e7fb9dc11a59b1ef892478c0e304028d6 100644 (file)
--- a/riscv/insns/amo_min.h
+++ b/riscv/insns/amo_min.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 sreg_t v = mmu.load_int64(RS1);
 mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
 RD = v;

diff --git a/riscv/insns/amo_minu.h b/riscv/insns/amo_minu.h
index 5af3b9da8e2c0dcd10e5b2203fbf03ed5381800b..c09c51aa13052d5197c25f7e0c8f02f00f86b6bc 100644 (file)
--- a/riscv/insns/amo_minu.h
+++ b/riscv/insns/amo_minu.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, std::min(RS2,v));
 RD = v;

diff --git a/riscv/insns/amo_or.h b/riscv/insns/amo_or.h
index df4f2fec5c559f09f0ff2410ad5d1ddb38748481..76a45086a5498c4c2783d9c2bead0b172880fa85 100644 (file)
--- a/riscv/insns/amo_or.h
+++ b/riscv/insns/amo_or.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 | v);
 RD = v;

diff --git a/riscv/insns/amo_swap.h b/riscv/insns/amo_swap.h
index 688905531fc0b0d820d945deee0a722f5284a354..43e353868f648976e0ba7afc849913ee6b3b4d7a 100644 (file)
--- a/riscv/insns/amo_swap.h
+++ b/riscv/insns/amo_swap.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2);
 RD = v;

diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h
index 84c1a712be2de1b17dd29b279f9e0c8141d4896f..68c04827a3704c45deea1bb47e9fee49aca62661 100644 (file)
--- a/riscv/insns/cvt_d_l.h
+++ b/riscv/insns/cvt_d_l.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
 FRD = i64_to_f64(RS1);

diff --git a/riscv/insns/cvt_l_d.h b/riscv/insns/cvt_l_d.h
index 2747d6776908dc9458e9195a108f828ee6749a28..bd460d57c0725c71e6391792841cbe9f825045bb 100644 (file)
--- a/riscv/insns/cvt_l_d.h
+++ b/riscv/insns/cvt_l_d.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
 RD = f64_to_i64_r_minMag(FRS1,true);

diff --git a/riscv/insns/cvt_l_s.h b/riscv/insns/cvt_l_s.h
index f5b053c09f11e6a4cf3a11510f64876c88f44704..1ed4594c045e033d43b424bbf3f298e2d384b8f2 100644 (file)
--- a/riscv/insns/cvt_l_s.h
+++ b/riscv/insns/cvt_l_s.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
 RD = f32_to_i64_r_minMag(FRS1,true);

diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h
index 79fbc97af4e130ba08d700a9e0b8080b67c8e0d4..f149229d860a3078453fb1dedef65267ddd4ab00 100644 (file)
--- a/riscv/insns/cvt_s_l.h
+++ b/riscv/insns/cvt_s_l.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
 FRD = i64_to_f32(RS1);

diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h
index 84c1a712be2de1b17dd29b279f9e0c8141d4896f..68c04827a3704c45deea1bb47e9fee49aca62661 100644 (file)
--- a/riscv/insns/cvtu_d_l.h
+++ b/riscv/insns/cvtu_d_l.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
 FRD = i64_to_f64(RS1);

diff --git a/riscv/insns/cvtu_l_d.h b/riscv/insns/cvtu_l_d.h
index 2747d6776908dc9458e9195a108f828ee6749a28..bd460d57c0725c71e6391792841cbe9f825045bb 100644 (file)
--- a/riscv/insns/cvtu_l_d.h
+++ b/riscv/insns/cvtu_l_d.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
 RD = f64_to_i64_r_minMag(FRS1,true);

diff --git a/riscv/insns/cvtu_l_s.h b/riscv/insns/cvtu_l_s.h
index f5b053c09f11e6a4cf3a11510f64876c88f44704..1ed4594c045e033d43b424bbf3f298e2d384b8f2 100644 (file)
--- a/riscv/insns/cvtu_l_s.h
+++ b/riscv/insns/cvtu_l_s.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
 RD = f32_to_i64_r_minMag(FRS1,true);

diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h
index 79fbc97af4e130ba08d700a9e0b8080b67c8e0d4..f149229d860a3078453fb1dedef65267ddd4ab00 100644 (file)
--- a/riscv/insns/cvtu_s_l.h
+++ b/riscv/insns/cvtu_s_l.h
@@ -1,4 +1,4 @@
-require64;
+require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
 FRD = i64_to_f32(RS1);

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 1f61cf161384a774a27d8ad2b692cded8528d571..aa671342ec5101732a516b0284687c16a366768c 100644 (file)
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,5 +1,9 @@
-require64;
 if(RS2 == 0 || (sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1))
-  RD = sreg_t(RS1) < 0 ? INT64_MIN : INT64_MAX;
+{
+  if(xpr64)
+    RD = sreg_t(RS1) < 0 ? INT64_MIN : INT64_MAX;
+  else
+    RD = sreg_t(RS1) < 0 ? sext32(INT32_MIN) : INT32_MAX;
+}
 else
-  RD = sreg_t(RS1) / sreg_t(RS2);
+  RD = sext_xprlen(sreg_t(RS1) / sreg_t(RS2));

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 86792a2010c462cf96599712a424a595d63dbc08..d4a4eca0720ec9f4acb7aa60fdbf621ac2dfd2b4 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,5 +1,4 @@
-require64;
 if(RS2 == 0)
   RD = UINT64_MAX;
 else
-  RD = RS1 / RS2;
+  RD = sext_xprlen(RS1 / RS2);

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 296bb9e16f52d11fa5d13a4332792d2724ae851b..4d64be3b1fbcbeaad90708e724d2cb93504a9341 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,4 +1,5 @@
-if(uint32_t(RS2) == 0)
-  RD = sext32(UINT32_MAX);
+require_xpr64;
+if(RS2 == 0)
+  RD = UINT64_MAX;
 else
-  RD = sext32(uint32_t(RS1)/uint32_t(RS2));
+  RD = sext32(RS1 / RS2);

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index bfc982a7a50329ad7eab76a3395cc8a34f94eb0f..9c732b51247106d9903e1815f0a879f63f80d486 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,4 +1,7 @@
-if(int32_t(RS2) == 0 || (int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1))
-  RD = sext32(int32_t(RS1) < 0 ? INT32_MIN : INT32_MAX);
+require_xpr64;
+// INT64_MIN/-1 corner case shouldn't occur in correct code, since
+// INT64_MIN is not a proper 32-bit signed value
+if(RS2 == 0 || (sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1))
+  RD = sext32(sreg_t(RS1) < 0 ? INT32_MIN : INT32_MAX);
 else
-  RD = sext32(int32_t(RS1)/int32_t(RS2));
+  RD = sext32(sreg_t(RS1) / sreg_t(RS2));

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 973a8b3bc25370d6d5b2094716a06a6bc41b0381..940d348f07171e6ba0532f63f5546614704587ed 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
-require64;
+require_xpr64;
 RD = mmu.load_int64(RS1+SIMM);

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
index 6209e6f79c1f7717644b9381cda9bbeca8188b0f..f3bd81e50ef3d050c59901687c2068b61ac8474b 100644 (file)
--- a/riscv/insns/mfcr.h
+++ b/riscv/insns/mfcr.h
@@ -15,4 +15,4 @@ switch(insn.rtype.rs2)
     val = -1;
 }
 
-RD = gprlen == 64 ? val : sext32(val);
+RD = sext_xprlen(val);

diff --git a/riscv/insns/mff_d.h b/riscv/insns/mff_d.h
index ba535619c949461a99dcc2c24a9eb115e52432a8..31be4cb14ad85882b993db22b3b1e3245b78fad8 100644 (file)
--- a/riscv/insns/mff_d.h
+++ b/riscv/insns/mff_d.h
@@ -1,3 +1,3 @@
-require64;
+require_xpr64;
 require_fp;
 RD = FRS2;

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 54c62edccfe80b0d496c696384233fdea20f4532..e9d5350c4cc3af953d297e3b48296dbe77bed4e8 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -45,4 +45,4 @@ switch(insn.rtype.rs2)
     val = -1;
 }
 
-RD = gprlen == 64 ? val : sext32(val);
+RD = sext_xprlen(val);

diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h
index 44daa9e38cbd12465089dee3175210dc7009e643..29792ec425b41048e960568fc37f712dcc13eeae 100644 (file)
--- a/riscv/insns/mtf_d.h
+++ b/riscv/insns/mtf_d.h
@@ -1,3 +1,3 @@
-require64;
+require_xpr64;
 require_fp;
 FRD = RS1;

diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index ff1e034007971a59342bc44f2108e7a39cfe2299..770d73388a2380b142e4f6b8524a60bef24628a5 100644 (file)
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1 @@
-require64;
-RD = RS1 * RS2;
+RD = sext_xprlen(RS1 * RS2);

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index ed9c1a822115c01a6a52836dc87e13fe7c244b9a..ceefccd91bad7b6a47c3a2a85337d4962fa36185 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,4 +1,8 @@
-require64;
-int64_t rb = RS1;
-int64_t ra = RS2;
-RD = (int128_t(rb) * int128_t(ra)) >> 64;
+if(xpr64)
+{
+  int64_t a = RS1;
+  int64_t b = RS2;
+  RD = (int128_t(a) * int128_t(b)) >> 64;
+}
+else
+  RD = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);

diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 17c610d672936fbad51371c46ff89ef9a187a20b..b6f45dd2b712f4e5d2d38dbab341a9c738e73a92 100644 (file)
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,2 +1,4 @@
-require64;
-RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64;
+if(xpr64)
+  RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64;
+else
+  RD = sext32((RS1 * RS2) >> 32);

diff --git a/riscv/insns/mulhuw.h b/riscv/insns/mulhuw.h
deleted file mode 100644 (file)
index 9260a24..0000000
--- a/riscv/insns/mulhuw.h
+++ /dev/null
@@ -1,2 +0,0 @@
-RD = sext32((RS1 * RS2) >> 32);
-

diff --git a/riscv/insns/mulhw.h b/riscv/insns/mulhw.h
deleted file mode 100644 (file)
index a47aa1e..0000000
--- a/riscv/insns/mulhw.h
+++ /dev/null
@@ -1,2 +0,0 @@
-RD = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);
-

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index 81285a22cf11c6fcab64c57d7632671aac516d29..7b0a934b68e20ee022e7c871e88dfb8210a413a4 100644 (file)
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
+require_xpr64;
 RD = sext32(RS1 * RS2);
-

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 1bc94f2556c165ebe7d687e031433808012ab6d5..db7e0a96465cd6b23d4e881937a72f640aa2ea50 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,5 +1,6 @@
-require64;
-if(RS2 == 0 || (sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1))
+if(RS2 == 0)
+  RD = RS1;
+else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
   RD = 0;
 else
-  RD = sreg_t(RS1) % sreg_t(RS2);
+  RD = sext_xprlen(sreg_t(RS1) % sreg_t(RS2));

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index 3b6c44f79aa822b816df1b81b3fee85dc797217e..04499ab3f40d3b4311227d2e36bd2bb08182153c 100644 (file)
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,5 +1,4 @@
-require64;
 if(RS2 == 0)
-  RD = 0;
+  RD = RS1;
 else
-  RD = RS1 % RS2;
+  RD = sext_xprlen(RS1 % RS2);

diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 820a396e011e016028f6c96525fe413efa2fb84d..ae28fa567ebe437f4fdbe1ad89d80e0f2f98df04 100644 (file)
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,4 +1,5 @@
-if(uint32_t(RS2) == 0)
-  RD = 0;
+require_xpr64;
+if(RS2 == 0)
+  RD = RS1;
 else
-  RD = sext32(uint32_t(RS1) % uint32_t(RS2));
+  RD = sext32(RS1 % RS2);

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index eb23ef1c4ac90a932f2a1d7aa1153b264fcae1f0..784baa392aa9674bf865e15ea5a991d3a8e35072 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,4 +1,9 @@
-if(int32_t(RS2) == 0 || (int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1))
+require_xpr64;
+// INT64_MIN/-1 corner case shouldn't occur in correct code, since
+// INT64_MIN is not a proper 32-bit signed value
+if(RS2 == 0)
+  RD = RS1;
+else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
   RD = 0;
 else
-  RD = sext32(int32_t(RS1) % int32_t(RS2));
+  RD = sext32(sreg_t(RS1) % sreg_t(RS2));

diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index f4ece21e50f66811417ddc1399378f9284f27358..2009149a4bc8d654b203e4e378bbd070b5724750 100644 (file)
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
-require64;
+require_xpr64;
 mmu.store_uint64(RS1+BIMM, RS2);

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index ae38f16b67892b763bf8ca287c82dc1c66b5866a..86eb96682ca3a1818f29ed18310415a9647fcaf1 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1,2 +1 @@
-require64;
-RD = RS1 << (RS2 & 0x3F);
+RD = sext_xprlen(RS1 << (RS2 & (xprlen-1)));

diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index f7ba310d3e3330192c9c9876214dd352081445ea..bfaf4307df06497c9ed10b455f4cc8398772c031 100644 (file)
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,2 +1,8 @@
-require64;
-RD = RS1 << SHAMT;
+if(xpr64)
+  RD = RS1 << SHAMT;
+else
+{
+  if(SHAMT & 0x20)
+    throw trap_illegal_instruction;
+  RD = sext32(RS1 << SHAMT);
+}

diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index 41be30f5c7d0784f0ca511b5c5d2afab965e6916..1f6e50dfb52195764c2d1aa21b504874f4073279 100644 (file)
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1 +1,2 @@
+require_xpr64;
 RD = sext32(RS1 << SHAMTW);

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index 90e5c4c9ed05dfbc1b56a459b8ff6372dbb665af..f3356d89f826b8c0d2a920e08d04be14b831fb13 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1 +1,2 @@
+require_xpr64;
 RD = sext32(RS1 << (RS2 & 0x1F));

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index 4a789164d8fcecc9b257d09ab4005cea776a5acf..8bbdc0972147b42611b16bbaa677b3737529e5c0 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1,2 +1 @@
-require64;
-RD = sreg_t(RS1) >> (RS2 & 0x3F);
+RD = sext_xprlen(sreg_t(RS1) >> (RS2 & (xprlen-1)));

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index 1f0dde2acddfa386733c04b0479f84b2b69f86d5..18fc55bf69ae64fa61ecdfee5b0dbfaeb1e03b85 100644 (file)
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,2 +1,8 @@
-require64;
-RD = sreg_t(RS1) >> SHAMT;
+if(xpr64)
+  RD = sreg_t(RS1) >> SHAMT;
+else
+{
+  if(SHAMT & 0x20)
+    throw trap_illegal_instruction;
+  RD = sext32(sreg_t(RS1) >> SHAMT);
+}

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 24a9eae4c4b74079186f8d05d8045af4764ac2da..42d0fc385248e5db4a17fadda8155a3044ef3fea 100644 (file)
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1 +1,2 @@
+require_xpr64;
 RD = sext32(sreg_t(RS1) >> SHAMTW);

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index f8946fbb3f2fd4d8b01c70c78cdea30dfc72d3f2..103f03a3184b4866864af29ffe3f89557831f3c0 100644 (file)
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1 +1,2 @@
+require_xpr64;
 RD = sext32(sreg_t(RS1) >> (RS2 & 0x1F));

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index 87138dab4f2ee591a18054008a9a5e509f5108b9..8230d2724b9c1d480c20a38c90dba7cbc7372249 100644 (file)
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,2 +1,4 @@
-require64;
-RD = RS1 >> (RS2 & 0x3F);
+if(xpr64)
+  RD = RS1 >> (RS2 & 0x3F);
+else
+  RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));

diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index e0d8ae079bf5541a470e36161c88404648ee22c6..5378fd1e57118756fbf8574ff5ddeeeb5c7ed8d2 100644 (file)
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,2 +1,8 @@
-require64;
-RD = RS1 >> SHAMT;
+if(xpr64)
+  RD = RS1 >> SHAMT;
+else
+{
+  if(SHAMT & 0x20)
+    throw trap_illegal_instruction;
+  RD = sext32((uint32_t)RS1 >> SHAMT);
+}

diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index 2a2bb31ee591616d14cb6e3abb29d779ff8ce613..c400507570fd3adc08fbd69191b5101b7a43f2b4 100644 (file)
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1 +1,2 @@
+require_xpr64;
 RD = sext32((uint32_t)RS1 >> SHAMTW);

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index a0058ae04a24fd0d0085876d19b83280179ab4a0..b206f7c86a24951364c0d5792f1bd191854ab9e1 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1,2 @@
+require_xpr64;
 RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));

diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index e7736c9e448e169ed6a12e4066c99e1f80770ccc..2b1e0570ad4213cce46ce84a1e78adf849ff7597 100644 (file)
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1,2 +1 @@
-require64;
-RD = RS1 - RS2;
+RD = sext_xprlen(RS1 - RS2);

diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h
index 958cc5d7a67b345d755c7a2615b0147ae35f6822..28db33481c28eebdd134eb103444432bac483ceb 100644 (file)
--- a/riscv/insns/subw.h
+++ b/riscv/insns/subw.h
@@ -1,2 +1,3 @@
+require_xpr64;
 RD = sext32(RS1 - RS2);
 

diff --git a/riscv/processor.cc b/riscv/processor.cc
index eed85da76154cadabd27b04d0ba6b88bf455df8d..6f3665305751de22b14d0448ce9510b986657d19 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -12,8 +12,8 @@
 processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   : sim(_sim), mmu(_mem,_memsz)
 {
-  memset(R,0,sizeof(R));
-  memset(FR,0,sizeof(FR));
+  memset(XPR,0,sizeof(XPR));
+  memset(FPR,0,sizeof(FPR));
   pc = 0;
   evec = 0;
   epc = 0;
@@ -26,7 +26,7 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   count = 0;
   compare = 0;
   interrupts_pending = 0;
-  set_sr(SR_S | (support_64bit ? SR_SX : 0));
+  set_sr(SR_S | SR_SX);  // SX ignored if 64b mode not supported
   set_fsr(0);
 
   memset(counters,0,sizeof(counters));
@@ -48,12 +48,14 @@ void processor_t::init(uint32_t _id)
 void processor_t::set_sr(uint32_t val)
 {
   sr = val & ~SR_ZERO;
-  if(!support_64bit)
-    sr &= ~(SR_SX | SR_UX);
-  if(!support_fp)
-    sr &= ~SR_EF;
-
-  gprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
+#ifndef RISCV_ENABLE_64BIT
+  sr &= ~(SR_SX | SR_UX);
+#endif
+#ifndef RISCV_ENABLE_64BIT
+  sr &= ~SR_EF;
+#endif
+
+  xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
 }
 
 void processor_t::set_fsr(uint32_t val)
@@ -86,7 +88,7 @@ void processor_t::step(size_t n, bool noisy)
       #include "execute.h"
   
       pc = npc;
-      R[0] = 0;
+      XPR[0] = 0;
 
       if(count++ == compare)
         interrupts_pending |= 1 << TIMER_IRQ;

diff --git a/riscv/processor.h b/riscv/processor.h
index 9ccfbb432558600578dc17ce1b1671909b6f42ba..b54803844f01a32a784b9712ee401f05e66aba5c 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -19,8 +19,8 @@ private:
   sim_t* sim;
 
   // architected state
-  reg_t R[NGPR];
-  freg_t FR[NFPR];
+  reg_t XPR[NXPR];
+  freg_t FPR[NFPR];
 
   // privileged control registers
   reg_t pc;
@@ -41,8 +41,8 @@ private:
   // unprivileged control registers
   uint32_t fsr;
 
-  // 32-bit or 64-bit mode (redundant with sr)
-  int gprlen;
+  // # of bits in an XPR (32 or 64). (redundant with sr)
+  int xprlen;
 
   // shared memory
   mmu_t mmu;

diff --git a/riscv/sim.cc b/riscv/sim.cc
index ffcb186bffae23f2903e0f9e21203a529528f2fd..f78802153808d84231c14b4a7fa9a1bac800fe38 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -163,10 +163,10 @@ reg_t sim_t::get_reg(const std::vector<std::string>& args)
 
   int p = atoi(args[0].c_str());
   int r = atoi(args[1].c_str());
-  if(p >= (int)procs.size() || r >= NGPR)
+  if(p >= (int)procs.size() || r >= NXPR)
     throw trap_illegal_instruction;
 
-  return procs[p].R[r];
+  return procs[p].XPR[r];
 }
 
 reg_t sim_t::get_freg(const std::vector<std::string>& args)
@@ -179,7 +179,7 @@ reg_t sim_t::get_freg(const std::vector<std::string>& args)
   if(p >= (int)procs.size() || r >= NFPR)
     throw trap_illegal_instruction;
 
-  return procs[p].FR[r];
+  return procs[p].FPR[r];
 }
 
 reg_t sim_t::get_tohost(const std::vector<std::string>& args)