(bdesc_2srg): Likewise.
(bdesc_1arg): Likewise.
+ * config/i386/i386.c (ix86_init_builtins): Correct return type
+ building v4hi_ftype_v4hi_int_int tree node.
+ (ix86_expand_sse_comi): Fix typo swapping operands.
+ Don't swap comparision condition, it is already swapped.
+ (ix86_expand_sse_compare): Before swapping operands
+ move operand 1 into new rtx and not the target rtx.
+ Don't swap comparison condition, it is already swapped.
+ Always check whether we need to create a new TARGET.
+
+ * config/i386/i386.md: (sse_comi) Fix typos.
+ (sse_ucomi): Likewise.
+ (cvtss2si): Fix operand 0 contraint.
+ (cvttss2si): Likewise.
+ (sse_unpckhps): Fix mode for operand 2.
+ (sse_unpcklps): Likewise.
+
2001-09-25 Graham Stott <grahams@redhat.com>
* sibcall.c (skip_copy_to_return_value): Tighten return value
tree_cons (NULL_TREE, integer_type_node,
endlink));
tree v4sf_ftype_v4sf_int
- = build_function_type (integer_type_node,
+ = build_function_type (V4SF_type_node,
tree_cons (NULL_TREE, V4SF_type_node,
tree_cons (NULL_TREE, integer_type_node,
endlink)));
hardware. */
if (d->flag)
{
- target = gen_reg_rtx (tmode);
- emit_move_insn (target, op1);
+ rtx tmp = gen_reg_rtx (mode1);
+ emit_move_insn (tmp, op1);
op1 = op0;
- op0 = target;
- comparison = swap_condition (comparison);
+ op0 = tmp;
}
- else if (! target
- || GET_MODE (target) != tmode
- || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
+
+ if (! target
+ || GET_MODE (target) != tmode
+ || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
target = gen_reg_rtx (tmode);
if (! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
rtx tmp = op1;
op1 = op0;
op0 = tmp;
- comparison = swap_condition (comparison);
}
target = gen_reg_rtx (SImode);
(match_operand:V4SF 1 "register_operand" "x")
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
- "comiss\t{%2, %0|%0, %2}"
+ "comiss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(define_insn "sse_ucomi"
(match_operand:V4SF 1 "register_operand" "x")
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
- "ucomiss\t{%2, %0|%0, %2}"
+ "ucomiss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")])
(const_int 0)
(const_int 3)
(const_int 1)]))
- (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
+ (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
(parallel [(const_int 0)
(const_int 2)
(const_int 1)
(const_int 2)
(const_int 1)
(const_int 3)]))
- (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
+ (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
(parallel [(const_int 2)
(const_int 0)
(const_int 3)
[(set_attr "type" "sse")])
(define_insn "cvtss2si"
- [(set (match_operand:SI 0 "register_operand" "=y")
+ [(set (match_operand:SI 0 "register_operand" "=r")
(vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
(parallel [(const_int 0)])))]
"TARGET_SSE"
[(set_attr "type" "sse")])
(define_insn "cvttss2si"
- [(set (match_operand:SI 0 "register_operand" "=y")
+ [(set (match_operand:SI 0 "register_operand" "=r")
(vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
(parallel [(const_int 0)])))]
"TARGET_SSE"