Add support for MIPS R6 evp and dvp instructions.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

gas/testsuite/
	* gas/mips/r6.s: Add evp and dvp instructions.
	* gas/mips/r6.d: Likewise.
	* gas/mips/r6-n32.d: Likewise.
	* gas/mips/r6-n64.d: Likewise.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2876e6334e35f7afa7c63007ddc229d2d5368660..1fd7362d16f4be11fb87d15b08b710558dd32546 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * gas/mips/r6.s: Add evp and dvp instructions.
+       * gas/mips/r6.d: Likewise.
+       * gas/mips/r6-n32.d: Likewise.
+       * gas/mips/r6-n64.d: Likewise.
+
 2015-03-13  Jiong Wang  <jiong.wang@arm.com>
 
        * gas/aarch64/diagnostic.s: New testcases.

diff --git a/gas/testsuite/gas/mips/r6-n32.d b/gas/testsuite/gas/mips/r6-n32.d
index d4e98590a99f53aefe956f2b72093bff349a68e3..acca6c4929b95cdd9a814c3e2d2a9d1b17af87df 100644 (file)
--- a/gas/testsuite/gas/mips/r6-n32.d
+++ b/gas/testsuite/gas/mips/r6-n32.d
@@ -493,4 +493,8 @@ Disassembly of section .text:
 0+0588 <[^>]*> f8040000        jalrc   a0
 0+058c <[^>]*> 04100000        nal
 0+0590 <[^>]*> 00000000        nop
+0+0594 <[^>]*> 41600004        evp
+0+0598 <[^>]*> 41600024        dvp
+0+059c <[^>]*> 41620004        evp     v0
+0+05a0 <[^>]*> 41620024        dvp     v0
        \.\.\.

diff --git a/gas/testsuite/gas/mips/r6-n64.d b/gas/testsuite/gas/mips/r6-n64.d
index e388e7a5c50db23a4c5e70db88a9287e9da7be90..10deeae5d910b183d546490e2001489e143842b8 100644 (file)
--- a/gas/testsuite/gas/mips/r6-n64.d
+++ b/gas/testsuite/gas/mips/r6-n64.d
@@ -749,4 +749,8 @@ Disassembly of section .text:
 0+0588 <[^>]*> f8040000        jalrc   a0
 0+058c <[^>]*> 04100000        nal
 0+0590 <[^>]*> 00000000        nop
+0+0594 <[^>]*> 41600004        evp
+0+0598 <[^>]*> 41600024        dvp
+0+059c <[^>]*> 41620004        evp     v0
+0+05a0 <[^>]*> 41620024        dvp     v0
        \.\.\.

diff --git a/gas/testsuite/gas/mips/r6.d b/gas/testsuite/gas/mips/r6.d
index 94ab611c9dfeaff6fe0dc06ce0783401543daf0a..cca10a7988bb0a1eba9e7e41a30efad579dd6416 100644 (file)
--- a/gas/testsuite/gas/mips/r6.d
+++ b/gas/testsuite/gas/mips/r6.d
@@ -492,4 +492,8 @@ Disassembly of section .text:
 0+0588 <[^>]*> f8040000        jalrc   a0
 0+058c <[^>]*> 04100000        nal
 0+0590 <[^>]*> 00000000        nop
+0+0594 <[^>]*> 41600004        evp
+0+0598 <[^>]*> 41600024        dvp
+0+059c <[^>]*> 41620004        evp     v0
+0+05a0 <[^>]*> 41620024        dvp     v0
        \.\.\.

diff --git a/gas/testsuite/gas/mips/r6.s b/gas/testsuite/gas/mips/r6.s
index e4ee0834071372138d3223b1a8b57ef2ad6327f5..0635066d10579a13ea5031730a5299d3dbdc71f3 100644 (file)
--- a/gas/testsuite/gas/mips/r6.s
+++ b/gas/testsuite/gas/mips/r6.s
@@ -261,6 +261,11 @@ new:       maddf.s $f0,$f1,$f2
        jalrc   $4
        nal
 
+       evp
+       dvp
+       evp     $2
+       dvp     $2
+
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
        .align  2
        .space  8

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8f2a473e0c4876454c0cb85db5b7d8365944a4d6..7608570116e43eea0735c38c641566b5556dc653 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
+
 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
        * s390-opc.c: Add new IBM z13 instructions.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0472b5bf24375c9c7d1755dcfc5bd540efce2f39..f43f9f5bbf31fba5d8182c79e22a5e89aee15bbb 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1147,6 +1147,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsubu",              "d,v,I",        0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3,             0,      0 },
 {"dvpe",               "",             0x41600001, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
 {"dvpe",               "t",            0x41600001, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
+{"dvp",                        "",             0x41600024, 0xffffffff, TRAP,                   0,              I37,            0,      0 },
+{"dvp",                        "t",            0x41600024, 0xffe0ffff, WR_1|TRAP,              0,              I37,            0,      0 },
 {"ei",                 "",             0x42000038, 0xffffffff, WR_C0,                  0,              EE,             0,      0 },
 {"ei",                 "",             0x41606020, 0xffffffff, WR_C0,                  0,              I33,            0,      0 },
 {"ei",                 "t",            0x41606020, 0xffe0ffff, WR_1|WR_C0,             0,              I33,            0,      0 },
@@ -1156,6 +1158,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"eretnc",             "",             0x42000058, 0xffffffff, NODS,                   0,              I36,            0,      0 },
 {"evpe",               "",             0x41600021, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
 {"evpe",               "t",            0x41600021, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
+{"evp",                        "",             0x41600004, 0xffffffff, TRAP,                   0,              I37,            0,      0 },
+{"evp",                        "t",            0x41600004, 0xffe0ffff, WR_1|TRAP,              0,              I37,            0,      0 },
 {"ext",                        "t,r,+A,+C",    0x7c000000, 0xfc00003f, WR_1|RD_2,              0,              I33,            0,      0 },
 {"exts32",             "t,r,+p,+s",    0x7000003b, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"exts",               "t,r,+P,+S",    0x7000003b, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 }, /* exts32 */