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whitespace cleanup
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 24 Oct 2023 17:16:06 +0000 (18:16 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:21 +0000 (19:26 +0000)
src/openpower/decoder/isa/test_syscall.py patch | blob | history

diff --git a/src/openpower/decoder/isa/test_syscall.py b/src/openpower/decoder/isa/test_syscall.py
index 6c782409bbcf34e399164a66ccbefdc43b2ea539..a1f42ba24b8af1f66023dcb95a8e05619ce2907d 100644 (file)
--- a/src/openpower/decoder/isa/test_syscall.py
+++ b/src/openpower/decoder/isa/test_syscall.py
@@ -70,7 +70,7 @@ class SyscallTestCase(FHDLTestCase):
         self.assertEqual(sim.msr, MSR)          # MSR changed to this by sc/trap
 
         print("SYSCALL SRR1", hex(int(SRR1)), hex(int(sim.spr['SRR1'])))
-        print("SYSCALL  MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR))
+        print("SYSCALL MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR))
         return sim
 
     def test_sc_getpid(self):