radeonsi: do not export VS outputs from vertex streams != 0

This affects for GS copy shaders. When an output is meant for vertex
stream != 0, then we don't have to make it available to the pixel
shader.

There is a minor inefficiency here because the GLSL varying packing pass
does not group varyings of the same vertex stream together, but it
shouldn't be important in practice.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 5a40c5ee91d13c87c8b1597a09c7a1ba982d762b..7c8fad1d6599feb8329ecef40099f3b53a7046e4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2394,6 +2394,12 @@ static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
                        break;
                }
 
+               if (outputs[i].vertex_stream[0] != 0 &&
+                   outputs[i].vertex_stream[1] != 0 &&
+                   outputs[i].vertex_stream[2] != 0 &&
+                   outputs[i].vertex_stream[3] != 0)
+                       export_param = false;
+
 handle_semantic:
                /* Select the correct target */
                switch(semantic_name) {