whoops one extra bit on the overflow test in mullw/mulld

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index 7edafee2d186920aaf5120d67408d54184170ed9..a3d054aacfe34063807c9a4ad68d0ea38b6433a1 100644 (file)
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -350,8 +350,8 @@ Pseudo-code:
 
     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
     RT <- prod
-    overflow <- ((prod[0:32] != 0x0_0000_0000) &
-                 (prod[0:32] != 0x1_ffff_ffff))
+    overflow <- ((prod[0:33] != 0x0_0000_0000) &
+                 (prod[0:33] != 0x1_ffff_ffff))
 
 Special Registers Altered:
 
@@ -564,8 +564,8 @@ Pseudo-code:
 
     prod[0:127] <- MULS((RA), (RB))
     RT <- prod[64:127]
-    overflow <- ((prod[0:64] != 0x0_0000_0000_0000_0000) &
-                 (prod[0:64] != 0x1_ffff_ffff_ffff_ffff))
+    overflow <- ((prod[0:65] != 0x0_0000_0000_0000_0000) &
+                 (prod[0:65] != 0x1_ffff_ffff_ffff_ffff))
 
 Special Registers Altered: