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Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values
authorCatherine <whitequark@whitequark.org>
Sat, 11 Dec 2021 16:24:47 +0000 (16:24 +0000)
committerGitHub <noreply@github.com>
Sat, 11 Dec 2021 16:24:47 +0000 (16:24 +0000)
write_verilog: dump zero width sigspecs correctly


Trivial merge