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Merge pull request #907 from YosysHQ/clifford/fix906
authorClifford Wolf <clifford@clifford.at>
Fri, 29 Mar 2019 23:09:42 +0000 (00:09 +0100)
committerGitHub <noreply@github.com>
Fri, 29 Mar 2019 23:09:42 +0000 (00:09 +0100)
Build Verilog parser with -DYYMAXDEPTH=100000


Trivial merge