void iris_math_div32_gpr0(struct iris_context *ice,
struct iris_batch *batch,
uint32_t D);
+void iris_math_add32_gpr0(struct iris_context *ice,
+ struct iris_batch *batch,
+ uint32_t x);
uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
uint64_t gpu_timestamp);
}
}
+void
+iris_math_add32_gpr0(struct iris_context *ice,
+ struct iris_batch *batch,
+ uint32_t x)
+{
+ emit_lri32(batch, CS_GPR(1), x);
+ emit_alu_add(batch, MI_ALU_R0, MI_ALU_R0, MI_ALU_R1);
+}
+
/*
* GPR0 = (GPR0 == 0) ? 0 : 1;
*/
lrm.MemoryAddress =
ro_bo(iris_resource_bo(so->offset.res), so->offset.offset);
}
+ if (so->base.buffer_offset)
+ iris_math_add32_gpr0(ice, batch, -so->base.buffer_offset);
iris_math_div32_gpr0(ice, batch, so->stride);
_iris_emit_lrr(batch, _3DPRIM_VERTEX_COUNT, CS_GPR(0));