Compilation fix after messy merge.

--HG--
extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472

diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 5f6a33565733685651e40b3b050dc068bc6704ce..83cdf73bcf56f5f54689a432f0208495a104832d 100755 (executable)
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1362,7 +1362,7 @@ class ControlRegOperand(Operand):
         bit_select = 0
         if (self.ctype == 'float' or self.ctype == 'double'):
             error(0, 'Attempt to read control register as FP')
-        base = 'xc->readMiscRegOperandWithEffect(%s)' % self.reg_spec
+        base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx
         if self.size == self.dflt_size:
             return '%s = %s;\n' % (self.base_name, base)
         else:

diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index ed0c41e61d5c384321f78c0572e3dbd01fd9f70f..1d9075a570f7cf0c6d18279e51aa931d81e31ee4 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -68,7 +68,7 @@ let {{
         decode_block = ROrImmDecode.subst(iop)
         exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm,
                 execute, faultCode, name, name + "Imm",
-                Name, Name + "Imm", opt_flags)
+                Name, Name + "Imm", asi, opt_flags)
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 6641d38bb7027e7d8edf5ea1999234e915ca4534..9c703d917f5def4deedfe788913818aec5cca86c 100644 (file)
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -47,8 +47,15 @@ string SparcISA::getMiscRegName(RegIndex index)
 {
     static::string miscRegName[NumMiscRegs] =
         {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
+         "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
+         "stick", "stick_cmpr",
+         "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
          "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
          "wstate",*/ "gl",
+         "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
+         "hstick_cmpr",
+         "fsr"};
+
     return miscRegName[index];
 }
 
@@ -59,8 +66,8 @@ enum RegMask
 
 void MiscRegFile::clear()
 {
-    y = 0;
-    ccr = 0;
+    //y = 0;
+    //ccr = 0;
     asi = 0;
     tick = ULL(1) << 63;
     fprs = 0;
@@ -77,11 +84,11 @@ void MiscRegFile::clear()
     tl = 0;
     pil = 0;
     cwp = 0;
-    cansave = 0;
-    canrestore = 0;
-    cleanwin = 0;
-    otherwin = 0;
-    wstate = 0;
+    //cansave = 0;
+    //canrestore = 0;
+    //cleanwin = 0;
+    //otherwin = 0;
+    //wstate = 0;
     gl = 0;
     //In a T1, bit 11 is apparently always 1
     hpstate = (1 << 11);
@@ -143,10 +150,10 @@ MiscReg MiscRegFile::readReg(int miscReg)
                (uint64_t)priContext << 32 |
                (uint64_t)secContext << 48;
 
-      case MISCREG_Y:
-        return y;
-      case MISCREG_CCR:
-        return ccr;
+      //case MISCREG_Y:
+      //  return y;
+      //case MISCREG_CCR:
+      //  return ccr;
       case MISCREG_ASI:
         return asi;
       case MISCREG_FPRS:
@@ -189,16 +196,16 @@ MiscReg MiscRegFile::readReg(int miscReg)
         return pil;
       case MISCREG_CWP:
         return cwp;
-      case MISCREG_CANSAVE:
-        return cansave;
-      case MISCREG_CANRESTORE:
-        return canrestore;
-      case MISCREG_CLEANWIN:
-        return cleanwin;
-      case MISCREG_OTHERWIN:
-        return otherwin;
-      case MISCREG_WSTATE:
-        return wstate;
+      //case MISCREG_CANSAVE:
+      //  return cansave;
+      //case MISCREG_CANRESTORE:
+      //  return canrestore;
+      //case MISCREG_CLEANWIN:
+      //  return cleanwin;
+      //case MISCREG_OTHERWIN:
+      //  return otherwin;
+      //case MISCREG_WSTATE:
+      //  return wstate;
       case MISCREG_GL:
         return gl;
 
@@ -369,12 +376,12 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 {
     switch (miscReg) {
-      case MISCREG_Y:
-        y = val;
-        break;
-      case MISCREG_CCR:
-        ccr = val;
-        break;
+//      case MISCREG_Y:
+//        y = val;
+//        break;
+//      case MISCREG_CCR:
+//        ccr = val;
+//        break;
       case MISCREG_ASI:
         asi = val;
         break;
@@ -436,21 +443,21 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
       case MISCREG_CWP:
         cwp = val;
         break;
-      case MISCREG_CANSAVE:
-        cansave = val;
-        break;
-      case MISCREG_CANRESTORE:
-        canrestore = val;
-        break;
-      case MISCREG_CLEANWIN:
-        cleanwin = val;
-        break;
-      case MISCREG_OTHERWIN:
-        otherwin = val;
-        break;
-      case MISCREG_WSTATE:
-        wstate = val;
-        break;
+//      case MISCREG_CANSAVE:
+//        cansave = val;
+//        break;
+//      case MISCREG_CANRESTORE:
+//        canrestore = val;
+//        break;
+//      case MISCREG_CLEANWIN:
+//        cleanwin = val;
+//        break;
+//      case MISCREG_OTHERWIN:
+//        otherwin = val;
+//        break;
+//      case MISCREG_WSTATE:
+//        wstate = val;
+//        break;
       case MISCREG_GL:
         gl = val;
         break;
@@ -666,23 +673,23 @@ void MiscRegFile::serialize(std::ostream & os)
 {
     SERIALIZE_SCALAR(pstate);
     SERIALIZE_SCALAR(tba);
-    SERIALIZE_SCALAR(y);
+//    SERIALIZE_SCALAR(y);
     SERIALIZE_SCALAR(pil);
     SERIALIZE_SCALAR(gl);
     SERIALIZE_SCALAR(cwp);
     SERIALIZE_ARRAY(tt, MaxTL);
-    SERIALIZE_SCALAR(ccr);
+//    SERIALIZE_SCALAR(ccr);
     SERIALIZE_SCALAR(asi);
     SERIALIZE_SCALAR(tl);
     SERIALIZE_ARRAY(tpc, MaxTL);
     SERIALIZE_ARRAY(tnpc, MaxTL);
     SERIALIZE_ARRAY(tstate, MaxTL);
     SERIALIZE_SCALAR(tick);
-    SERIALIZE_SCALAR(cansave);
-    SERIALIZE_SCALAR(canrestore);
-    SERIALIZE_SCALAR(otherwin);
-    SERIALIZE_SCALAR(cleanwin);
-    SERIALIZE_SCALAR(wstate);
+//    SERIALIZE_SCALAR(cansave);
+//    SERIALIZE_SCALAR(canrestore);
+//    SERIALIZE_SCALAR(otherwin);
+//    SERIALIZE_SCALAR(cleanwin);
+//    SERIALIZE_SCALAR(wstate);
     SERIALIZE_SCALAR(fsr);
     SERIALIZE_SCALAR(fprs);
     SERIALIZE_SCALAR(hpstate);
@@ -725,23 +732,23 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 {
     UNSERIALIZE_SCALAR(pstate);
     UNSERIALIZE_SCALAR(tba);
-    UNSERIALIZE_SCALAR(y);
+//    UNSERIALIZE_SCALAR(y);
     UNSERIALIZE_SCALAR(pil);
     UNSERIALIZE_SCALAR(gl);
     UNSERIALIZE_SCALAR(cwp);
     UNSERIALIZE_ARRAY(tt, MaxTL);
-    UNSERIALIZE_SCALAR(ccr);
+//    UNSERIALIZE_SCALAR(ccr);
     UNSERIALIZE_SCALAR(asi);
     UNSERIALIZE_SCALAR(tl);
     UNSERIALIZE_ARRAY(tpc, MaxTL);
     UNSERIALIZE_ARRAY(tnpc, MaxTL);
     UNSERIALIZE_ARRAY(tstate, MaxTL);
     UNSERIALIZE_SCALAR(tick);
-    UNSERIALIZE_SCALAR(cansave);
-    UNSERIALIZE_SCALAR(canrestore);
-    UNSERIALIZE_SCALAR(otherwin);
-    UNSERIALIZE_SCALAR(cleanwin);
-    UNSERIALIZE_SCALAR(wstate);
+//    UNSERIALIZE_SCALAR(cansave);
+//    UNSERIALIZE_SCALAR(canrestore);
+//    UNSERIALIZE_SCALAR(otherwin);
+//    UNSERIALIZE_SCALAR(cleanwin);
+//    UNSERIALIZE_SCALAR(wstate);
     UNSERIALIZE_SCALAR(fsr);
     UNSERIALIZE_SCALAR(fprs);
     UNSERIALIZE_SCALAR(hpstate);

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index ace916f5b28fd0783f158c332b7fb2fc4d3a165e..8ede2421ac1c5c8ba58938760179da88d6c8e471 100644 (file)
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -169,8 +169,8 @@ namespace SparcISA
       private:
 
         /* ASR Registers */
-        uint64_t y;            // Y (used in obsolete multiplication)
-        uint8_t        ccr;            // Condition Code Register
+        //uint64_t y;          // Y (used in obsolete multiplication)
+        //uint8_t ccr;         // Condition Code Register
         uint8_t asi;           // Address Space Identifier
         uint64_t tick;         // Hardware clock-tick counter
         uint8_t        fprs;           // Floating-Point Register State
@@ -195,11 +195,11 @@ namespace SparcISA
         uint8_t tl;            // Trap Level
         uint8_t pil;           // Process Interrupt Register
         uint8_t cwp;           // Current Window Pointer
-        uint8_t cansave;       // Savable windows
-        uint8_t canrestore;    // Restorable windows
-        uint8_t cleanwin;      // Clean windows
-        uint8_t otherwin;      // Other windows
-        uint8_t wstate;                // Window State
+        //uint8_t cansave;     // Savable windows
+        //uint8_t canrestore;  // Restorable windows
+        //uint8_t cleanwin;    // Clean windows
+        //uint8_t otherwin;    // Other windows
+        //uint8_t wstate;              // Window State
         uint8_t gl;             // Global level register
 
         /** Hyperprivileged Registers */

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index f69b40ffb8ccb58801d551ee11ed9e94264ea897..a6e6a8bd30a341eff88a04fe3445f5afbf6b0330 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -115,7 +115,7 @@ class TLB : public SimObject
     void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
 
-    void TLB::clearUsedBits();
+    void clearUsedBits();
 
 
     void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);