* and a texture-compatible base buffer in other cases
*
*/
-
if (templat->bind & (PIPE_BIND_SCANOUT | PIPE_BIND_DEPTH_STENCIL)) {
if (screen->specs.pixel_pipes > 1 && !screen->specs.single_buffer)
layout |= ETNA_LAYOUT_BIT_MULTI;
if (screen->specs.can_supertile)
layout |= ETNA_LAYOUT_BIT_SUPER;
} else if (VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE) &&
- /* RS can't tile 1 byte per pixel formats, will have to CPU tile,
- * which doesn't support super-tiling
- */
- util_format_get_blocksize(templat->format) > 1) {
+ etna_resource_hw_tileable(screen->specs.use_blt, templat)) {
layout |= ETNA_LAYOUT_BIT_SUPER;
}
#include "etnaviv_internal.h"
#include "etnaviv_tiling.h"
#include "pipe/p_state.h"
+#include "util/format/u_format.h"
#include "util/list.h"
#include "util/set.h"
#include "util/u_helpers.h"
PIPE_BIND_SAMPLER_VIEW;
}
+static inline bool
+etna_resource_hw_tileable(bool use_blt, const struct pipe_resource *pres)
+{
+ if (use_blt)
+ return true;
+
+ /* RS can only tile 16bpp or 32bpp formats */
+ return util_format_get_blocksize(pres->format) == 2 ||
+ util_format_get_blocksize(pres->format) == 4;
+}
+
static inline struct etna_resource *
etna_resource(struct pipe_resource *p)
{
rsc = etna_resource(rsc->texture);
} else if (rsc->ts_bo ||
(rsc->layout != ETNA_LAYOUT_LINEAR &&
- util_format_get_blocksize(format) > 1 &&
+ etna_resource_hw_tileable(ctx->specs.use_blt, prsc) &&
/* HALIGN 4 resources are incompatible with the resolve engine,
* so fall back to using software to detile this resource. */
rsc->halign != TEXTURE_HALIGN_FOUR)) {