Add more info

diff --git a/meetings/sync_up/sync_up_2023-11-28.mdwn b/meetings/sync_up/sync_up_2023-11-28.mdwn
index 9c377256cc4912bbe1261d14bbca405a60d714e4..02a223a2bb640dd2cc3645df6a10bb36740b92a0 100644 (file)
--- a/meetings/sync_up/sync_up_2023-11-28.mdwn
+++ b/meetings/sync_up/sync_up_2023-11-28.mdwn
@@ -26,13 +26,17 @@
 - RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
 - The first step is to make modifications to `svanalysis.py` to classify the RISC-V instructions.
 - Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>
-- Invent an opcode format?
 
 
 # Dmitry
 
 * Check whether RISC-V have their own way of describing the instructions
   (likely they do).
+* Familiarise yourself with
+[svanalysis.py](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;h=21778ad02d78c4f7ef5b6df93e096f4abbe365ad;hb=HEAD),
+as we will need a similar tool for RISC-V.
+* Check what RISC-V support in binutils looks like. *Needed for confirming
+the details of the RISC-V binutils grant*.
 
 # Sadoon
 
@@ -60,6 +64,8 @@
   [bug #1183](https://bugs.libre-soc.org/show_bug.cgi?id=1183)
   which jacob also noted for sv.cmpi/ff needed on bigmul.
 
+* Guide Dmitry on svanalysis.py.
+
 # Shriya
 
 -