ARM: Warn about and ignore accesses to DCCISW.

This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 897ecf3e36d19a1df5e544c9f095c51f5c1a8fd9..5498a84b07ea405429959e643854ecc77c70b07a 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -94,6 +94,9 @@ def format McrMrc15() {{
             return new NopInst(machInst);
         } else if (miscReg == NUM_MISCREGS) {
             return new Unknown(machInst);
+        } else if (miscReg == MISCREG_DCCISW) {
+            return new WarnUnimplemented(isRead ? "mrc dccisw" : "mcr dcisw",
+                                         machInst);
         } else {
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 8fce26b2c0e207243cb5075db5d4bc4d3680a8cd..c65b55a52b1c9122c6d9ac58ca7798e9cda5cbfd 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -82,6 +82,7 @@ namespace ArmISA
         // CP15 registers
         MISCREG_CP15_START,
         MISCREG_SCTLR = MISCREG_CP15_START,
+        MISCREG_DCCISW,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR,
@@ -136,7 +137,6 @@ namespace ArmISA
         MISCREG_CP15DMB,
         MISCREG_DCCMVAU,
         MISCREG_DCCIMVAC,
-        MISCREG_DCCISW,
         MISCREG_CONTEXTIDR,
         MISCREG_TPIDRURW,
         MISCREG_TPIDRURO,
@@ -158,7 +158,7 @@ namespace ArmISA
         "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
         "spsr_mon", "spsr_und", "spsr_abt",
         "fpsr", "fpsid", "fpscr", "fpexc",
-        "sctlr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
+        "sctlr", "dccisw", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@@ -167,7 +167,7 @@ namespace ArmISA
         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
         "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
         "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
-        "cp15dsb", "cp15dmb", "dccmvau", "dccimvac", "dccisw",
+        "cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "nop", "raz"
     };