cpu: Fix vector renaming bug
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 17 Feb 2020 10:45:43 +0000 (10:45 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 19 Feb 2020 14:54:24 +0000 (14:54 +0000)
The following patch:

https://gem5-review.googlesource.com/c/public/gem5/+/25009

moved initialization of vecMode out of initializing list.
In this way regFile gets initialized with an invalid initial renaming
mode.

Change-Id: Ib7bab9eaac0f5850fd3b3151584132f809a641e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25430
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/cpu/o3/cpu.cc

index e29dcf0caa81212ce1c9f3366c7889d1dd62abab..e2c72700892d97bd1157d4a9ef96ac1258df7740 100644 (file)
@@ -99,6 +99,9 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
       iew(this, params),
       commit(this, params),
 
+      /* It is mandatory that all SMT threads use the same renaming mode as
+       * they are sharing registers and rename */
+      vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
       regFile(params->numPhysIntRegs,
               params->numPhysFloatRegs,
               params->numPhysVecRegs,
@@ -128,12 +131,6 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
       system(params->system),
       lastRunningCycle(curCycle())
 {
-    auto *the_isa = dynamic_cast<TheISA::ISA *>(params->isa[0]);
-    assert(the_isa);
-    /* It is mandatory that all SMT threads use the same renaming mode as
-     * they are sharing registers and rename */
-    vecMode = RenameMode<TheISA::ISA>::init(the_isa);
-
     if (!params->switched_out) {
         _status = Running;
     } else {