X86: Make the IO ports work using extra physical address lines. Add a serial port.

--HG--
extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 5b21dbb39d3e04b33d3adcc64003acd074fdb99d..c8916841bc56a41f56ddcfc16a63ba579183201d 100644 (file)
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2006-2008 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -155,6 +155,10 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
 
     return self
 
+def x86IOAddress(port):
+    IO_address_space_base = 0x1000000000000000
+    return IO_address_space_base + port;
+
 def makeLinuxX86System(mem_mode, mdesc = None):
     self = LinuxX86System()
     if not mdesc:
@@ -163,10 +167,23 @@ def makeLinuxX86System(mem_mode, mdesc = None):
     self.readfile = mdesc.script()
 
     # Physical memory
-    self.membus = Bus(bus_id=0)
+    self.membus = Bus(bus_id=1)
     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.physmem.port = self.membus.port
 
+    # North Bridge
+    self.iobus = Bus(bus_id=0)
+    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+    self.bridge.side_a = self.iobus.port
+    self.bridge.side_b = self.membus.port
+
+    # Serial port and console
+    self.console = SimConsole()
+    self.com_1 = Uart8250()
+    self.com_1.pio_addr = x86IOAddress(0x3f8)
+    self.com_1.pio = self.iobus.port
+    self.com_1.sim_console = self.console
+
     # Platform
     self.opteron = Opteron()
 

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 08c6216154c1a47f547e04f7ae86272e41ee091b..2e6ea4a22ba1d0b700ca42b99a3fb05037239e53 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -470,6 +470,16 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
             //overlapping.
             req->setPaddr(regNum * sizeof(MiscReg));
             return NoFault;
+        } else if (prefix == IntAddrPrefixIO) {
+            // TODO If CPL > IOPL or in virtual mode, check the I/O permission
+            // bitmap in the TSS.
+
+            Addr IOPort = vaddr & ~IntAddrPrefixMask;
+            // Make sure the address fits in the expected 16 bit IO address
+            // space.
+            assert(!(IOPort & ~0xFFFF));
+            req->setPaddr(PhysAddrPrefixIO | IOPort);
+            return NoFault;
         } else {
             panic("Access to unrecognized internal address space %#x.\n",
                     prefix);

diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index dd9258db048a725961612c98f7b548e8d93d5ed4..dc71de5003d7a1103f978b44fce1839d701581ab 100644 (file)
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -87,6 +87,8 @@ namespace X86ISA
     const Addr IntAddrPrefixCPUID = ULL(0x100000000);
     const Addr IntAddrPrefixMSR = ULL(0x200000000);
     const Addr IntAddrPrefixIO = ULL(0x300000000);
+
+    const Addr PhysAddrPrefixIO = ULL(0x1000000000000000);
 }
 
 #endif //__ARCH_X86_X86TRAITS_HH__