add extra (dummy) mul operation, 0*0

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 99d75192e6b49ff88d0612dba90a0ceee566846c..3d8fdfa9e1188f918a63df184ba5b02443617683 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -183,6 +183,7 @@ class DecoderTestCase(FHDLTestCase):
                      ]
         """
         lst = ["fmuls 3, 1, 2", # 7.0 * -9.8 = -68.6
+               "fmuls 29,12,8", # test
                      ]
 
         fprs = [0] * 32