+2020-08-12 Joe Ramsay <joe.ramsay@.arm.com>
+
+ * config/tc-arm.c (do_neon_cvt_1): Parse vcvtne as vcvt-ne for
+ NS_FD shape when MVE is present
+ * testsuite/gas/arm/mve-vcvtne-it-bad.d: New test.
+ * testsuite/gas/arm/mve-vcvtne-it-bad.l: New test.
+ * testsuite/gas/arm/mve-vcvtne-it-bad.s: New test.
+ * testsuite/gas/arm/mve-vcvtne-it.d: New test.
+ * testsuite/gas/arm/mve-vcvtne-it.s: New test.
+
2020-08-12 Alex Coplan <alex.coplan@arm.com>
* testsuite/gas/aarch64/mpam-bad.d: New test.
return;
}
+ if ((rs == NS_FD || rs == NS_QQI) && mode == neon_cvt_mode_n
+ && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ {
+ /* We are dealing with vcvt with the 'ne' condition. */
+ inst.cond = 0x1;
+ inst.instruction = N_MNEM_vcvt;
+ do_neon_cvt_1 (neon_cvt_mode_z);
+ return;
+ }
+
/* VFP rather than Neon conversions. */
if (flavour >= neon_cvt_flavour_first_fp)
{
NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
}
- else if (mode == neon_cvt_mode_n)
- {
- /* We are dealing with vcvt with the 'ne' condition. */
- inst.cond = 0x1;
- inst.instruction = N_MNEM_vcvt;
- do_neon_cvt_1 (neon_cvt_mode_z);
- return;
- }
/* fall through. */
case NS_DDI:
{
--- /dev/null
+# name: MVE vcvtne instruction outside of IT block
+# as: -march=armv8.1-m.main+mve.fp+fp.dp
+# error_output: mve-vcvtne-it-bad.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:3: Error: thumb conditional instruction should be in IT block -- `vcvtne.s32.f64 s13,d8'
--- /dev/null
+.syntax unified
+.text
+vcvtne.s32.f64 s13, d8
--- /dev/null
+# name: Armv8.1-M Mainline vcvt instruction in it block (with MVE)
+# as: -march=armv8.1-m.main+mve.fp+fp.dp
+# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+^[^>]*> bf18[ ]+it[ ]+ne
+^[^>]*> eefd 6bc8[ ]+vcvtne.s32.f64[ ]+s13, d8
\ No newline at end of file
--- /dev/null
+.syntax unified
+.text
+it ne
+vcvtne.s32.f64 s13, d8