Revert BRAM WRITE_MODE changes.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v
index 2a23b2553fa3c8125e0aef0b783068d34c046927..7ea49158d27cbf83e99877432eb77539bcc392a4 100644 (file)
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/brams_map.v
@@ -30,8 +30,8 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
                .RAM_MODE("SDP"),
                .READ_WIDTH_A(72),
                .WRITE_WIDTH_B(72),
-               .WRITE_MODE_A("WRITE_FIRST"),
-               .WRITE_MODE_B("WRITE_FIRST"),
+               .WRITE_MODE_A("READ_FIRST"),
+               .WRITE_MODE_B("READ_FIRST"),
                .IS_CLKARDCLK_INVERTED(!CLKPOL2),
                .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
                `include "brams_init_36.vh"
@@ -95,8 +95,8 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
                .RAM_MODE("SDP"),
                .READ_WIDTH_A(36),
                .WRITE_WIDTH_B(36),
-               .WRITE_MODE_A("WRITE_FIRST"),
-               .WRITE_MODE_B("WRITE_FIRST"),
+               .WRITE_MODE_A("READ_FIRST"),
+               .WRITE_MODE_B("READ_FIRST"),
                .IS_CLKARDCLK_INVERTED(!CLKPOL2),
                .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
                `include "brams_init_18.vh"
@@ -171,8 +171,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
                        .READ_WIDTH_B(CFG_DBITS),
                        .WRITE_WIDTH_A(CFG_DBITS),
                        .WRITE_WIDTH_B(CFG_DBITS),
-                       .WRITE_MODE_A("WRITE_FIRST"),
-                       .WRITE_MODE_B("WRITE_FIRST"),
+                       .WRITE_MODE_A("READ_FIRST"),
+                       .WRITE_MODE_B("READ_FIRST"),
                        .IS_CLKARDCLK_INVERTED(!CLKPOL2),
                        .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
                        `include "brams_init_36.vh"
@@ -209,8 +209,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
                        .READ_WIDTH_B(CFG_DBITS),
                        .WRITE_WIDTH_A(CFG_DBITS),
                        .WRITE_WIDTH_B(CFG_DBITS),
-                       .WRITE_MODE_A("WRITE_FIRST"),
-                       .WRITE_MODE_B("WRITE_FIRST"),
+                       .WRITE_MODE_A("READ_FIRST"),
+                       .WRITE_MODE_B("READ_FIRST"),
                        .IS_CLKARDCLK_INVERTED(!CLKPOL2),
                        .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
                        `include "brams_init_32.vh"
@@ -285,8 +285,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
                        .READ_WIDTH_B(CFG_DBITS),
                        .WRITE_WIDTH_A(CFG_DBITS),
                        .WRITE_WIDTH_B(CFG_DBITS),
-                       .WRITE_MODE_A("WRITE_FIRST"),
-                       .WRITE_MODE_B("WRITE_FIRST"),
+                       .WRITE_MODE_A("READ_FIRST"),
+                       .WRITE_MODE_B("READ_FIRST"),
                        .IS_CLKARDCLK_INVERTED(!CLKPOL2),
                        .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
                        `include "brams_init_18.vh"
@@ -323,8 +323,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
                        .READ_WIDTH_B(CFG_DBITS),
                        .WRITE_WIDTH_A(CFG_DBITS),
                        .WRITE_WIDTH_B(CFG_DBITS),
-                       .WRITE_MODE_A("WRITE_FIRST"),
-                       .WRITE_MODE_B("WRITE_FIRST"),
+                       .WRITE_MODE_A("READ_FIRST"),
+                       .WRITE_MODE_B("READ_FIRST"),
                        .IS_CLKARDCLK_INVERTED(!CLKPOL2),
                        .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
                        `include "brams_init_16.vh"