on scalar operation, sign-extend / zero-extend to full reg width

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index d80fb0890f82b0e1577b689356bb082e9c27954c..684952f1a472fa9596133ee05a6f364ec9b33a7f 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -84,15 +84,27 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
     }
     if (xlen != bitwidth)
     {
+        char *report = "";
         uint64_t data = _insn->p->get_state()->XPR[reg];
         uint64_t mask = ((1UL<<bitwidth)-1UL) << (shift*bitwidth);
         wval = (uint64_t)(wval << (shift*bitwidth)); // element within reg-block
         wval &= mask;
-        uint64_t ndata = data & (uint64_t)(~mask); // masks off the right bits
-        wval |= ndata;
-        fprintf(stderr, "writereg %ld bitwidth %d offs %d shift %d %lx " \
+        uint64_t ndata = data;
+        if (spec.isvec) {
+            ndata = data & (uint64_t)(~mask); // masks off right bits
+            wval |= ndata;
+        } else {
+            if (_insn->signextended) {
+                wval = sext_bwid(wval, bitwidth);
+                report = "s";
+            } else {
+                wval = zext_bwid(wval, bitwidth);
+                report = "z";
+            }
+        }
+        fprintf(stderr, "writereg %s %ld bitwidth %d offs %d shift %d %lx " \
                         " %lx %lx %lx\n",
-                        spec.reg, bitwidth, offs, shift, data,
+                        report, spec.reg, bitwidth, offs, shift, data,
                         ndata, mask, wval);
     }
     STATE.XPR.write(reg, wval);