/* Translate TGSI to our internal representation */
ttr.compiler = &compiler.Base;
ttr.info = &fs->info;
+ ttr.use_half_swizzles = TRUE;
r300_tgsi_to_rc(&ttr, fs->state.tokens);
for (i = 0; i < 4; i++) {
if (imm->u[i].Float == 0.0f) {
swizzle |= RC_SWIZZLE_ZERO << (i * 3);
- } else if (imm->u[i].Float == 0.5f) {
+ } else if (imm->u[i].Float == 0.5f && ttr->use_half_swizzles) {
swizzle |= RC_SWIZZLE_HALF << (i * 3);
} else if (imm->u[i].Float == 1.0f) {
swizzle |= RC_SWIZZLE_ONE << (i * 3);
}
}
-void r300_tgsi_to_rc(struct tgsi_to_rc * ttr, const struct tgsi_token * tokens)
+void r300_tgsi_to_rc(struct tgsi_to_rc * ttr,
+ const struct tgsi_token * tokens)
{
struct tgsi_parse_context parser;
unsigned imm_index = 0;
#ifndef R300_TGSI_TO_RC_H
#define R300_TGSI_TO_RC_H
+#include "pipe/p_compiler.h"
+
struct radeon_compiler;
struct tgsi_full_declaration;
int immediate_offset;
struct swizzled_imms * imms_to_swizzle;
unsigned imms_to_swizzle_count;
+
+ /* Vertex shaders have no half swizzles, and no way to handle them, so
+ * until rc grows proper support, indicate if they're safe to use. */
+ boolean use_half_swizzles;
};
void r300_tgsi_to_rc(struct tgsi_to_rc * ttr, const struct tgsi_token * tokens);
/* Translate TGSI to our internal representation */
ttr.compiler = &compiler.Base;
ttr.info = &vs->info;
+ ttr.use_half_swizzles = FALSE;
r300_tgsi_to_rc(&ttr, vs->state.tokens);