projects / nmigen.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: be4c39a)
vendor.xilinx_series7: use STARTUPE2, not STARTUPE3.
authorDarrell Harmon <dlharmon@users.noreply.github.com>
Wed, 21 Aug 2019 22:25:55 +0000 (16:25 -0600)
committerwhitequark <cz@m-labs.hk>
Wed, 21 Aug 2019 22:25:55 +0000 (22:25 +0000)
STARTUPE3 is for Ultrascale.

nmigen/vendor/xilinx_7series.py patch | blob | history

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 26b18ecbbe33a55947a0253a909950d9d739b985..a7620ec5f8a306f799cf87c8a59dfac053d28548 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -136,7 +136,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
 
             m = Module()
             ready = Signal()
-            m.submodules += Instance("STARTUPE3", o_EOS=ready)
+            m.submodules += Instance("STARTUPE2", o_EOS=ready)
             m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
             m.submodules += Instance("BUFGCE", i_CE=ready, i_I=clk_i, o_O=ClockSignal("sync"))
             if self.default_rst is not None: