(no commit message)

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 80dca134a376a981761e295482048993e863f72b..203f81bc4612259ce3c1328f8c7449fe5dbfafac 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -155,13 +155,23 @@ and therefore have no value are marked with 'NOT'
 
 ## Images of wires on FPGA and on STLINKV2
 
-[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="250x" ]]                                    
+Image of JTAG jumper wire connections on ULX3S FPGA side
 
-## Questions
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] 
 
-Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG?
+Image of JTAG jumper wire connections on STLINKV2 side
 
-Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
+(same orientation as JTAG pinout documentation)
+
+[[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]                                    
+
+Image of JTAG jumper wire connections on STLINKV2 side
+
+(opposite orientation as JTAG pinout documentation, 
+
+same orientation as 'ST' text on STLINKV2 device)
+
+[[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]                                    
 
 # STLinkV2 connector