radeonsi: define SGPR register numbers

Instead of hardcoding them.

Signed-off-by: Christian König <deathsimple@vodafone.de>

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pm4.c b/src/gallium/drivers/radeonsi/radeonsi_pm4.c
index 8268f9148088ceb54c8bd27365840fa4b0a7d741..ea0a1bd1aecc318d3c99185faa0cd8c22a906ee7 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_pm4.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.c
@@ -106,9 +106,10 @@ void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw)
        si_pm4_cmd_add(state, dw);
 }
 
-void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned reg)
+void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx)
 {
        unsigned offs = state->last_pm4 + 1;
+       unsigned reg = base + idx * 4;
 
        /* Bail if no data was added */
        if (state->ndw == offs) {

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pm4.h b/src/gallium/drivers/radeonsi/radeonsi_pm4.h
index 2b32ffb8155dbe6ab7fd7e0d806c49f43f42adeb..ef327d65915259c9881fe9964f63b8904f252654 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_pm4.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.h
@@ -71,7 +71,7 @@ void si_pm4_add_bo(struct si_pm4_state *state,
 
 void si_pm4_sh_data_begin(struct si_pm4_state *state);
 void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw);
-void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned reg);
+void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx);
 
 void si_pm4_inval_shader_cache(struct si_pm4_state *state);
 void si_pm4_inval_texture_cache(struct si_pm4_state *state);

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 57950a7a46e246d2a55f9d6129b5c699ac1a987a..75cb7e120b7b264e953916fb3f5281cd6e9630c7 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -196,10 +196,7 @@ static void declare_input_vs(
        unsigned chan;
 
        /* Load the T list */
-       /* XXX: Communicate with the rest of the driver about which SGPR the T#
-        * list pointer is going to be stored in.  Hard code to SGPR[6:7] for
-        * now */
-       t_list_ptr = use_sgpr(base->gallivm, SGPR_CONST_PTR_V4I32, 6);
+       t_list_ptr = use_sgpr(base->gallivm, SGPR_CONST_PTR_V4I32, SI_SGPR_VERTEX_BUFFER);
 
        t_offset = lp_build_const_int32(base->gallivm, input_index);
 
@@ -251,10 +248,7 @@ static void declare_input_fs(
         * [32:16] ParamOffset
         *
         */
-       /* XXX: This register number must be identical to the S_00B02C_USER_SGPR
-        * register field value
-        */
-       LLVMValueRef params = use_sgpr(base->gallivm, SGPR_I32, 6);
+       LLVMValueRef params = use_sgpr(base->gallivm, SGPR_I32, SI_PS_NUM_USER_SGPR);
 
 
        /* XXX: Is this the input_index? */
@@ -373,9 +367,7 @@ static LLVMValueRef fetch_constant(
                return bitcast(bld_base, type, load);
        }
 
-       /* XXX: Assume the pointer to the constant buffer is being stored in
-        * SGPR[0:1] */
-       const_ptr = use_sgpr(base->gallivm, SGPR_CONST_PTR_F32, 0);
+       const_ptr = use_sgpr(base->gallivm, SGPR_CONST_PTR_F32, SI_SGPR_CONST);
 
        /* XXX: This assumes that the constant buffer is not packed, so
         * CONST[0].x will have an offset of 0 and CONST[1].x will have an
@@ -652,14 +644,14 @@ static void tex_fetch_args(
                                                         0, LP_CHAN_ALL);
 
        /* Resource */
-       ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V8I32, 4);
+       ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V8I32, SI_SGPR_RESOURCE);
        offset = lp_build_const_int32(bld_base->base.gallivm,
                                  emit_data->inst->Src[1].Register.Index);
        emit_data->args[2] = build_indexed_load(bld_base->base.gallivm,
                                                ptr, offset);
 
        /* Sampler */
-       ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V4I32, 2);
+       ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V4I32, SI_SGPR_SAMPLER);
        offset = lp_build_const_int32(bld_base->base.gallivm,
                                  emit_data->inst->Src[1].Register.Index);
        emit_data->args[3] = build_indexed_load(bld_base->base.gallivm,

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index aa2888ccf3000427c6b583d50cacbd94ed73fc7b..688db57cca16f1aa29c3dd391a39551848e4be72 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -29,6 +29,14 @@
 #ifndef RADEONSI_SHADER_H
 #define RADEONSI_SHADER_H
 
+#define SI_SGPR_CONST          0
+#define SI_SGPR_SAMPLER                2
+#define SI_SGPR_RESOURCE       4
+#define SI_SGPR_VERTEX_BUFFER  6
+
+#define SI_VS_NUM_USER_SGPR    8
+#define SI_PS_NUM_USER_SGPR    6
+
 struct si_shader_io {
        unsigned                name;
        int                     sid;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 8d198483dc184dd4d6b36bcdb00e820118cbc6e7..b6b23065b94e32f923cbebad16735c9fcb6ce136 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2278,7 +2278,7 @@ static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
                        pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
        }
 
-       si_pm4_sh_data_end(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4);
+       si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_RESOURCE);
 
 out:
        si_pm4_set_state(rctx, ps_sampler_views, pm4);
@@ -2345,7 +2345,7 @@ static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **
                        si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
                }
        }
-       si_pm4_sh_data_end(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2);
+       si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_SAMPLER);
 
        if (border_color_table) {
                uint64_t va_offset =
@@ -2382,7 +2382,7 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint i
        struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
        struct si_pm4_state *pm4;
        uint64_t va_offset;
-       uint32_t offset;
+       uint32_t reg, offset;
 
        /* Note that the state tracker can unbind constant buffers by
         * passing NULL here.
@@ -2404,14 +2404,16 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint i
 
        switch (shader) {
        case PIPE_SHADER_VERTEX:
-               si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset);
-               si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32);
+               reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4;
+               si_pm4_set_reg(pm4, reg, va_offset);
+               si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
                si_pm4_set_state(rctx, vs_const, pm4);
                break;
 
        case PIPE_SHADER_FRAGMENT:
-               si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset);
-               si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32);
+               reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4;
+               si_pm4_set_reg(pm4, reg, va_offset);
+               si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
                si_pm4_set_state(rctx, ps_const, pm4);
                break;
 

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index db8f17fd36ccae4de9e83b6d4d66366d24ac0d0a..a431afef74a1c86905c53f77d658447a4835eb66 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -78,7 +78,7 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
        si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
        si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
 
-       num_user_sgprs = 8;
+       num_user_sgprs = SI_VS_NUM_USER_SGPR;
        num_sgprs = shader->num_sgprs;
        if (num_user_sgprs > num_sgprs)
                num_sgprs = num_user_sgprs;
@@ -207,7 +207,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
        si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
        si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
 
-       num_user_sgprs = 6;
+       num_user_sgprs = SI_PS_NUM_USER_SGPR;
        num_sgprs = shader->num_sgprs;
        if (num_user_sgprs > num_sgprs)
                num_sgprs = num_user_sgprs;
@@ -462,7 +462,7 @@ static void si_vertex_buffer_update(struct r600_context *rctx)
                        bound[ve->vertex_buffer_index] = true;
                }
        }
-       si_pm4_sh_data_end(pm4, R_00B148_SPI_SHADER_USER_DATA_VS_6);
+       si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
        si_pm4_set_state(rctx, vertex_buffers, pm4);
 }