desc->buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
- assert(count <= SI_NUM_VERTEX_BUFFERS);
+ assert(count <= SI_MAX_ATTRIBS);
for (i = 0; i < count; i++) {
struct pipe_vertex_element *ve = &velems->elements[i];
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
return 16384;
case PIPE_SHADER_CAP_MAX_INPUTS:
- return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
+ return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
case PIPE_SHADER_CAP_MAX_TEMPS:
struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct si_shader *shader = ctx->shader;
- LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
+ LLVMTypeRef params[SI_NUM_PARAMS + SI_MAX_ATTRIBS], v3i32;
LLVMTypeRef returns[16+32*4];
unsigned i, last_sgpr, num_params, num_return_sgprs;
unsigned num_returns = 0;
switch (ctx->type) {
case PIPE_SHADER_VERTEX:
- params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
+ params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_MAX_ATTRIBS);
params[SI_PARAM_BASE_VERTEX] = ctx->i32;
params[SI_PARAM_START_INSTANCE] = ctx->i32;
params[SI_PARAM_DRAWID] = ctx->i32;
/* Common VS bits between the shader key and the prolog key. */
struct si_vs_prolog_bits {
- unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS];
+ unsigned instance_divisors[SI_MAX_ATTRIBS];
};
/* Common VS bits between the shader key and the epilog key. */