- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
# License: BSD
from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.xilinx import XilinxPlatform
+from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):
- return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
+ bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
+ return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi)
+
+ def do_finalize(self, fragment):
+ XilinxPlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
def __init__(self):
MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io)
+
+ def do_finalize(self, fragment):
+ MicrosemiPlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk50", 0, loose=True), 1e9/50e6)
+ self.add_period_constraint(self.lookup_request("clk50", 1, loose=True), 1e9/50e6)
def create_programmer(self):
return USBBlaster()
+
+ def do_finalize(self, fragment):
+ AlteraPlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
def create_programmer(self):
- return VivadoProgrammer()
+ return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
- try:
- self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
- except ConstraintError:
- pass
+ self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
def create_programmer(self):
return IceStormProgrammer()
+
+ def do_finalize(self, fragment):
+ LatticePlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
# This file is Copyright (c) 2015 Yann Sionneau <ys@m-labs.hk>
from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.xilinx import XilinxPlatform
+from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
- return VivadoProgrammer()
+ return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
- try:
- self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
- except ConstraintError:
- pass
- try:
- self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
- except ConstraintError:
- pass
- try:
- self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
- except ConstraintError:
- pass
+ self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/125e6)
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
+ self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6)
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
</ispXCF>
"""
return LatticeProgrammer(_xcf_template)
+
+ def do_finalize(self, fragment):
+ LatticePlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
-from litex.build.xilinx.programmer import FpgaProg
+from litex.build.xilinx.programmer import XC3SProg
# IOs ----------------------------------------------------------------------------------------------
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
def create_programmer(self):
- return FpgaProg()
+ return XC3SProg(cable="ftdi")
+
+ def do_finalize(self, fragment):
+ XilinxPlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk32", loose=True), 1e9/32e6)
+ self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
# License: BSD
from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.xilinx import XilinxPlatform
+from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
def __init__(self, device="xc7a35t"):
assert device in ["xc7a35t", "xc7a100t"]
XilinxPlatform.__init__(self, device + "-fgg484-2", _io, toolchain="vivado")
+
+ def create_programmer(self):
+ bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
+ return OpenOCD("openocd_netv2_rpi.cfg", bscan_spi)
+
+ def do_finalize(self, fragment):
+ XilinxPlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/50e6)
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
- return VivadoProgrammer()
+ return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit")
+
+ def do_finalize(self, fragment):
+ XilinxPlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/50e6)
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
-
def create_programmer(self):
- return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
+ return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
except ConstraintError:
pass
+
+ def do_finalize(self, fragment):
+ XilinxPlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/125e6)
def create_programmer(self):
return TinyProgProgrammer()
+
+ def do_finalize(self, fragment):
+ LatticePlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk16", loose=True), 1e9/16e6)
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import UJProg
# IOs ----------------------------------------------------------------------------------------------
Subsignal("n", Pins("C10")),
IOStandard("LVCMOS33")
),
+
+ ("usb", 0,
+ Subsignal("d_p", Pins("D15")),
+ Subsignal("d_n", Pins("E15")),
+ Subsignal("pullup", Pins("B12 C12")),
+ IOStandard("LVCMOS33")
+ ),
]
# Platform -----------------------------------------------------------------------------------------
def __init__(self, device="LFE5U-45F", **kwargs):
LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
+
+ def create_programmer(self):
+ return UJProg()
+
+ def do_finalize(self, fragment):
+ LatticePlatform.do_finalize(self, fragment)
+ self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
-from litex.build.lattice.programmer import LatticeProgrammer
+from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
# IOs ----------------------------------------------------------------------------------------------
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
+ def create_programmer(self):
+ return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")
+
def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
- except ConstraintError:
- pass
- try:
- self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
- except ConstraintError:
- pass
+ self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
+import os
import argparse
from migen import *
# Build --------------------------------------------------------------------------------------------
def main():
- parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
+ parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
- parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
- parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+ parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build(**vivado_build_argdict(args))
+ builder.build(**vivado_build_argdict(args), run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
+import os
import argparse
from migen import *
# Clk / Rst
clk50 = platform.request("clk50")
- platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
+import os
import argparse
from migen import *
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
if __name__ == "__main__":
main()
# with more features, examples to run C/Rust code on the RISC-V CPU and documentation can be found
# at: https://github.com/icebreaker-fpga/icebreaker-litex-examples
+import os
import argparse
from migen import *
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
- parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash")
- parser.add_argument("--flash", action="store_true", help="Load Bitstream")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
+ parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash")
+ parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
- if args.flash:
- flash(args.bios_flash_offset)
-
soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bin"))
+
+ if args.flash:
+ flash(args.bios_flash_offset)
if __name__ == "__main__":
main()
# This file is Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
# License: BSD
+import os
import argparse
from migen import *
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on KC705")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
- parser.add_argument("--with-ethernet", action="store_true",
- help="enable Ethernet support")
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
+import os
import argparse
from migen import *
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on KCU105")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
- parser.add_argument("--with-ethernet", action="store_true",
- help="enable Ethernet support")
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
# License: BSD
+import os
import argparse
from fractions import Fraction
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
+import os
import argparse
from migen import *
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
- parser.add_argument("--with-ethernet", action="store_true",
- help="enable Ethernet support")
- parser.add_argument("--with-spi-xip", action="store_true",
- help="enable SPI XIP support")
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+ parser.add_argument("--with-spi-xip", action="store_true", help="Enable SPI XIP support")
args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet, with_spi_xip=args.with_spi_xip, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
+import os
import argparse
from migen import *
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
- parser.add_argument("--sys-clk-freq", default=75e6,
- help="system clock frequency (default=75MHz)")
- parser.add_argument("--with-ethernet", action="store_true",
- help="enable Ethernet support")
- parser.add_argument("--with-spi-sdcard", action="store_true",
- help="enable SPI-mode SDCard support")
- parser.add_argument("--with-sdcard", action="store_true",
- help="enable SDCard support")
+ parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)")
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+ parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support")
+ parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support")
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
raise ValueError("'--with-spi-sdcard' and '--with-sdcard' are mutually exclusive!")
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
+import os
import argparse
from migen import *
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
- parser.add_argument("--with-ethernet", action="store_true",
- help="enable Ethernet support")
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
# License: BSD
+import os
import argparse
import importlib
def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
builder_args(parser)
soc_core_args(parser)
- parser.add_argument("--with-ethernet", action="store_true",
- help="enable Ethernet support")
- parser.add_argument("platform",
- help="module name of the platform to build for")
- parser.add_argument("--gateware-toolchain", default=None,
- help="FPGA gateware toolchain used for build")
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+ parser.add_argument("platform", help="Module name of the platform to build for")
+ parser.add_argument("--gateware-toolchain", default=None, help="FPGA gateware toolchain used for build")
args = parser.parse_args()
platform_module = importlib.import_module(args.platform)
platform = platform_module.Platform()
soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
- builder.build()
+ builder.build(run=args.build)
if __name__ == "__main__":
# This file is Copyright (c) 2018 David Shah <dave@ds0.me>
# License: BSD
+import os
import argparse
import sys
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
- def __init__(self, platform, sys_clk_freq):
+ def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# Clk / Rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
- platform.add_period_constraint(clk25, 1e9/25e6)
# PLL
self.submodules.pll = pll = ECP5PLL()
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
+ # USB PLL
+ if with_usb_pll:
+ self.submodules.usb_pll = usb_pll = ECP5PLL()
+ usb_pll.register_clkin(clk25, 25e6)
+ self.clock_domains.cd_usb_12 = ClockDomain()
+ self.clock_domains.cd_usb_48 = ClockDomain()
+ usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
+ usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
+
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
- self.submodules.crg = _CRG(platform, sys_clk_freq)
+ with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
+ self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
- parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
- help="gateware toolchain to use, trellis (default) or diamond")
- parser.add_argument("--device", dest="device", default="LFE5U-45F",
- help="FPGA device, ULX3S can be populated with LFE5U-12F, LFE5U-25F, LFE5U-45F (default) or LFE5U-85F")
- parser.add_argument("--sys-clk-freq", default=50e6,
- help="system clock frequency (default=50MHz)")
- parser.add_argument("--sdram-module", default="MT48LC16M16",
- help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
+ parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+ parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
+ parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)")
+ parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
- builder.build(**builder_kargs)
+ builder.build(**builder_kargs, run=args.build)
+
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf"))
if __name__ == "__main__":
main()
# This file is Copyright (c) 2018-2019 David Shah <dave@ds0.me>
# License: BSD
+import os
import argparse
from migen import *
# Clk / Rst
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
- platform.add_period_constraint(clk100, 1e9/100e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
- parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
- help="gateware toolchain to use, trellis (default) or diamond")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
+ parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
- parser.add_argument("--sys-clk-freq", default=75e6,
- help="system clock frequency (default=75MHz)")
- parser.add_argument("--with-ethernet", action="store_true",
- help="enable Ethernet support")
+ parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)")
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
- builder.build(**builder_kargs)
+ builder.build(**builder_kargs, run=args.build)
+
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf"))
if __name__ == "__main__":
main()
projects / litex.git / commitdiff