shorten words

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 82c87a6a1169c54cce834e97f577a1254a16481c..33072e9d9228af239988af8cf4e858fed92c23ed 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -125,7 +125,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 
 * No new Interrupt types are required.
   (**No modifications to existing Power ISA are required either**).
-* GPR FPR and CR Field Register numbers are extended to 128.  A future
+* GPR FPR and CR Field Register extend to 128.  A future
   version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx]
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)
 * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding,