memset(ipr, 0, sizeof(ipr));
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
int
flattenIntIndex(int reg) const
void setIdleProcess(Addr idle, ThreadContext *tc);
public:
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace Kernel
return ppn << PageShift;
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace AlphaISA
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
- void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void loadState(CheckpointIn &cp) override;
void initState();
void argsInit(int intSize, int pageSize);
/**
* Serialization stuff
*/
- void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serializeSymtab(CheckpointOut &cp) const override;
+ void unserializeSymtab(CheckpointIn &cp) override;
/** Override startup() to provide a path to call setupFuncEvents()
*/
static Fault checkCacheability(RequestPtr &req, bool itb = false);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
// Most recently used page table entries
TlbEntry *EntryCache[3];
: BaseISADevice() {}
~DummyISADevice() {}
- void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
+ void setMiscReg(int misc_reg, MiscReg val) override;
+ MiscReg readMiscReg(int misc_reg) override;
};
}
ArmV8KvmCPU(ArmV8KvmCPUParams *params);
virtual ~ArmV8KvmCPU();
- void dump() M5_ATTR_OVERRIDE;
+ void dump() override;
protected:
- void updateKvmState() M5_ATTR_OVERRIDE;
- void updateThreadContext() M5_ATTR_OVERRIDE;
+ void updateKvmState() override;
+ void updateThreadContext() override;
protected:
/** Mapping between integer registers in gem5 and KVM */
BaseArmKvmCPU(BaseArmKvmCPUParams *params);
virtual ~BaseArmKvmCPU();
- void startup() M5_ATTR_OVERRIDE;
+ void startup() override;
protected:
- Tick kvmRun(Tick ticks) M5_ATTR_OVERRIDE;
+ Tick kvmRun(Tick ticks) override;
/** Cached state of the IRQ line */
KvmGic(const KvmGicParams *p);
~KvmGic();
- void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
- void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
+ void startup() override { verifyMemoryMode(); }
+ void drainResume() override { verifyMemoryMode(); }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(Checkpoint *cp, const std::string &sec) override;
public: // PioDevice
AddrRangeList getAddrRanges() const { return addrRanges; }
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
public: // BaseGic
- void sendInt(uint32_t num) M5_ATTR_OVERRIDE;
- void clearInt(uint32_t num) M5_ATTR_OVERRIDE;
+ void sendInt(uint32_t num) override;
+ void clearInt(uint32_t num) override;
- void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
- void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
+ void sendPPInt(uint32_t num, uint32_t cpu) override;
+ void clearPPInt(uint32_t num, uint32_t cpu) override;
protected:
/**
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(longDescFormat);
SERIALIZE_SCALAR(pfn);
paramOut(cp, "domain", domain_);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(longDescFormat);
UNSERIALIZE_SCALAR(pfn);
void addEventProbe(unsigned int id, SimObject *obj, const char *name);
public: // SimObject and related interfaces
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
public: // ISA Device interface
* @param misc_reg Register number (see miscregs.hh)
* @param val Value to store
*/
- void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
+ void setMiscReg(int misc_reg, MiscReg val) override;
/**
* Read a register within the PMU.
*
* @param misc_reg Register number (see miscregs.hh)
* @return Register value.
*/
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
+ MiscReg readMiscReg(int misc_reg) override;
protected: // PMU register types and constants
BitUnion32(PMCR_t)
: ProbeListenerArgBase(pm, name),
pmu(_pmu), id(_id) {}
- void notify(const uint64_t &val) M5_ATTR_OVERRIDE
+ void notify(const uint64_t &val) override
{
pmu.handleEvent(id, val);
}
listeners.reserve(4);
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Add an event count to the counter and check for overflow.
bool haveLargeAsid64() const { return _haveLargeAsid64; }
/** Checks if all state is cleared and if so, completes drain */
void completeDrain();
- DrainState drain() M5_ATTR_OVERRIDE;
- virtual void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ virtual void drainResume() override;
virtual BaseMasterPort& getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID);
bool callFromS2);
Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
/**
* Get the table walker master port. This is used for migrating
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Decoder.hh"
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(flags);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(flags);
} // namespace ArmISA
-__hash_namespace_begin
+namespace std {
template<>
struct hash<ArmISA::ExtMachInst> :
};
-__hash_namespace_end
+}
#endif
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(_pc);
SERIALIZE_SCALAR(_npc);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(_pc);
UNSERIALIZE_SCALAR(_npc);
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_upc);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_upc);
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_nnpc);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_nnpc);
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_upc);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_upc);
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
fatal("Serialization of Interrupts Unimplemented for MIPS");
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
fatal("Unserialization of Interrupts Unimplemented for MIPS");
}
static Fault checkCacheability(RequestPtr &req);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();
Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();
};
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
namespace PowerISA
} // PowerISA namespace
-__hash_namespace_begin
+namespace std {
template<>
struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
};
};
-__hash_namespace_end
+}
#endif // __ARCH_POWER_TYPES_HH__
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
SERIALIZE_SCALAR(intStatus);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
UNSERIALIZE_SCALAR(intStatus);
void clear();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void startup(ThreadContext *tc) {}
* Serialization stuff
*/
public:
- void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serializeSymtab(CheckpointOut &cp) const override;
+ void unserializeSymtab(CheckpointIn &cp) override;
/** reset binary symbol table */
SymbolTable *resetSymtab;
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Give an entry id, read that tlb entries' tte */
uint64_t TteRead(int entry);
#define __ARCH_X86_DECODER_HH__
#include <cassert>
+#include <unordered_map>
#include <vector>
#include "arch/x86/regs/misc.hh"
typedef DecodeCache::AddrMap<Decoder::InstBytes> DecodePages;
DecodePages *decodePages;
- typedef m5::hash_map<CacheKey, DecodePages *> AddrCacheMap;
+ typedef std::unordered_map<CacheKey, DecodePages *> AddrCacheMap;
AddrCacheMap addrCacheMap;
DecodeCache::InstMap *instMap;
- typedef m5::hash_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
+ typedef std::unordered_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
static InstCacheMap instCacheMap;
public:
/*
* Serialization.
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/*
* Old functions needed for compatability but which will be phased out
return reg;
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void startup(ThreadContext *tc);
return (1 << logBytes);
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
/** The size of each level of the page table expressed in base 2
#ifndef __ARCH_X86_REG_MSR_HH__
#define __ARCH_X86_REG_MSR_HH__
+#include <unordered_map>
+
#include "arch/x86/regs/misc.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
namespace X86ISA
{
-typedef
m5::hash_map<Addr, MiscRegIndex> MsrMap;
+typedef
std::unordered_map<Addr, MiscRegIndex> MsrMap;
/**
* Map between MSR addresses and their corresponding misc registers.
TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Get the table walker master port. This is used for
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
#include "base/cprintf.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
}
-__hash_namespace_begin
+namespace std {
template<>
struct hash<X86ISA::ExtMachInst> {
size_t operator()(const X86ISA::ExtMachInst &emi) const {
emi.stackSize ^ emi.dispSize;
};
};
-__hash_namespace_end
+}
// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
// and UNSERIALIZE_SCALAR.
#include "arch/x86/regs/misc.hh"
#include "arch/x86/types.hh"
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#ifndef __BASE_COMPILER_HH__
#define __BASE_COMPILER_HH__
-// gcc C++11 status: http://gcc.gnu.org/projects/cxx0x.html
-// clang C++11 status: http://clang.llvm.org/cxx_status.html
// http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html
-/* Support for override control (final/override) */
-#undef M5_COMP_HAS_OVERRIDE_CONTROL
-
-#if defined(__GNUC__) && !defined(__clang__) /* Check for gcc */
-
-# define M5_GCC_VERSION(maj, min) \
- (__GNUC__ > (maj) || (__GNUC__ == (maj) && __GNUC_MINOR__ >= (min)))
-
-# define M5_COMP_HAS_OVERRIDE_CONTROL M5_GCC_VERSION(4, 7)
-
-#elif defined(__clang__) /* Check for clang */
-
-# define M5_COMP_HAS_OVERRIDE_CONTROL __has_feature(cxx_override_control)
-
-#else
-# error "Need to define compiler options in base/compiler.hh"
-#endif
-
-
-#if M5_COMP_HAS_OVERRIDE_CONTROL
-# define M5_ATTR_FINAL final
-# define M5_ATTR_OVERRIDE override
-#else
-# define M5_ATTR_FINAL
-# define M5_ATTR_OVERRIDE
-#endif
-
#if defined(__GNUC__) // clang or gcc
# define M5_ATTR_NORETURN __attribute__((noreturn))
# define M5_DUMMY_RETURN
#include <map>
#include <memory>
#include <string>
+#include <unordered_map>
#include <vector>
#include "base/loader/symtab.hh"
-#include "base/hashmap.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/AnnotateQ.hh"
/**
* Provide a hash function for the CPI Id type
*/
-__hash_namespace_begin
+namespace std {
template <>
struct hash<std::pair<std::string, uint64_t> >
{
}
};
-__hash_namespace_end
+}
class CPA : SimObject
{
uint8_t cpu;
bool dump;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
typedef std::shared_ptr<AnnotateData> AnnDataPtr;
uint64_t conId;
// Convert state strings into state ids
- typedef m5::hash_map<std::string, int> SCache;
+ typedef std::unordered_map<std::string, int> SCache;
typedef std::vector<SCache> StCache;
// Convert sm and queue name,id into queue id
typedef std::pair<std::string, uint64_t> Id;
- typedef m5::hash_map<Id, int> IdHCache;
+ typedef std::unordered_map<Id, int> IdHCache;
typedef std::vector<IdHCache> IdCache;
// Hold mapping of sm and queues to output python
typedef std::map<int, int> LinkMap;
// SC Links
- typedef m5::hash_map<Id, AnnDataPtr> ScHCache;
+ typedef std::unordered_map<Id, AnnDataPtr> ScHCache;
typedef std::vector<ScHCache> ScCache;
void dump(bool all);
void dumpKey();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // !CP_ANNOTATE
virtual ~FrameBuffer();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Resize the frame buffer.
+++ /dev/null
-/*
- * Copyright (c) 2012 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Andreas Hansson
- */
-
-#ifndef __HASHMAP_HH__
-#define __HASHMAP_HH__
-
-// we stick with defines here until gcc >= 4.7 and clang >= 3.2 is
-// adopted as these are the minimum versions to support variadic
-// templates and template aliasing
-#define hash_map unordered_map
-#define hash_multimap unordered_multimap
-#define hash_set unordered_set
-#define hash_multiset unordered_multiset
-
-// gcc >= 4.4 or clang with libc++ no longer rely on the transitional
-// tr1 namespace
-#include <unordered_map>
-#include <unordered_set>
-#define __hash_namespace std
-#define __hash_namespace_begin namespace std {
-#define __hash_namespace_end }
-
-namespace m5 {
- using ::__hash_namespace::hash_multimap;
- using ::__hash_namespace::hash_multiset;
- using ::__hash_namespace::hash_map;
- using ::__hash_namespace::hash_set;
- using ::__hash_namespace::hash;
-}
-
-#endif // __HASHMAP_HH__
#include <fstream>
#include <list>
#include <string>
+#include <unordered_map>
#include <vector>
-#include "base/hashmap.hh"
-
/**
* @file
* Declaration of IniFile object.
class Section
{
/// EntryTable type. Map of strings to Entry object pointers.
- typedef m5::hash_map<std::string, Entry *> EntryTable;
+ typedef std::unordered_map<std::string, Entry *> EntryTable;
EntryTable table; ///< Table of entries.
mutable bool referenced; ///< Has this section been used?
};
/// SectionTable type. Map of strings to Section object pointers.
- typedef m5::hash_map<std::string, Section *> SectionTable;
+ typedef std::unordered_map<std::string, Section *> SectionTable;
protected:
/// Hash of section names to Section object pointers.
bool queued() { return queue != 0; }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
class PollQueue
return dist(gen);
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
extern Random random_mt;
{ }
void logMessage(Tick when, const std::string &name,
- const std::string &message) M5_ATTR_OVERRIDE;
+ const std::string &message) override;
- std::ostream &getOstream() M5_ATTR_OVERRIDE { return stream; }
+ std::ostream &getOstream() override { return stream; }
};
/** Get the current global debug logger. This takes ownership of the given
static const PixelConverter pixelConverter;
public:
- void setDirty() M5_ATTR_OVERRIDE;
- void frameBufferResized() M5_ATTR_OVERRIDE;
+ void setDirty() override;
+ void frameBufferResized() override;
};
#endif
virtual void startup();
virtual void regStats();
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
void registerThreadContexts();
*
* @param os The stream to serialize to.
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
/**
* Reconstruct the state of this object from a checkpoint.
* @param cp The checkpoint use.
* @param section The section name of this object.
*/
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) override;
/**
* Serialize a single thread.
Counter numLoad;
Counter startNumLoad;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
- void wakeup(ThreadID tid) M5_ATTR_OVERRIDE { }
+ void wakeup(ThreadID tid) override { }
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
void syscall(int64_t callnum) { }
#ifndef __CPU_DECODE_CACHE_HH__
#define __CPU_DECODE_CACHE_HH__
+#include <unordered_map>
+
#include "arch/isa_traits.hh"
#include "arch/types.hh"
-#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/static_inst_fwd.hh"
{
/// Hash for decoded instructions.
-typedef m5::hash_map<TheISA::ExtMachInst, StaticInstPtr> InstMap;
+typedef std::unordered_map<TheISA::ExtMachInst, StaticInstPtr> InstMap;
/// A sparse map from an Addr to a Value, stored in page chunks.
template<class Value>
Value items[TheISA::PageBytes];
};
// A map of cache pages which allows a sparse mapping.
- typedef typename
m5::hash_map<Addr, CachePage *> PageMap;
+ typedef typename
std::unordered_map<Addr, CachePage *> PageMap;
typedef typename PageMap::iterator PageIt;
// Mini cache of recent lookups.
PageIt recent[2];
/// Attempt to find the CacheePage which goes with a particular
/// address. First check the small cache of recent results, then
- /// actually look in the hash_map.
+ /// actually look in the hash map.
/// @param addr The address to look up.
CachePage *
getPage(Addr addr)
* This implementation of dump calls InstPBTrace to output the contents to a
* protobuf file
*/
- void dump() M5_ATTR_OVERRIDE;
+ void dump() override;
protected:
InstPBTrace& tracer;
InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
StaticInstPtr si, TheISA::PCState pc, const
- StaticInstPtr mi = NULL) M5_ATTR_OVERRIDE;
+ StaticInstPtr mi = NULL) override;
protected:
/** One output stream for the entire simulation.
void startup();
void regStats();
- void serializeThread(CheckpointOut &cp,
- ThreadID tid) const M5_ATTR_OVERRIDE;
- void unserializeThread(CheckpointIn &cp,
- ThreadID tid) M5_ATTR_OVERRIDE;
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *cpu);
MasterPort &getDataPort() { return dataPort; }
MasterPort &getInstPort() { return instPort; }
- void wakeup(ThreadID tid = 0) M5_ATTR_OVERRIDE;
+ void wakeup(ThreadID tid = 0) override;
void activateContext(ThreadID thread_num);
void suspendContext(ThreadID thread_num);
void deallocateContext(ThreadID thread_num);
void startup();
/** @{ */
- void dump() const M5_ATTR_OVERRIDE;
+ void dump() const override;
void dumpFpuRegs() const;
void dumpIntRegs() const;
void dumpSpecRegs() const;
/** Starting, waking and initialisation */
void init();
void startup();
- void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
+ void wakeup(ThreadID tid) override;
Addr dbg_vtophys(Addr addr);
Counter totalInsts() const;
Counter totalOps() const;
- void serializeThread(CheckpointOut &cp,
- ThreadID tid) const M5_ATTR_OVERRIDE;
- void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
/** Serialize pipeline data */
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);
/** Drain interface */
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
/** Signal from Pipeline that MinorCPU should signal that a drain
* is complete and set its drainState */
void signalDrainDone();
* stages and pipeline advance) */
void evaluate();
- void countCycles(Cycles delta) M5_ATTR_OVERRIDE
+ void countCycles(Cycles delta) override
{
cpu.ppCycles->notify(delta);
}
/** Is the CPU draining? */
bool isDraining() const { return drainState() == DrainState::Draining; }
- void serializeThread(CheckpointOut &cp,
- ThreadID tid) const M5_ATTR_OVERRIDE;
- void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
public:
/** Executes a syscall.
/** Starts draining the CPU's pipeline of all instructions in
* order to stop all memory accesses. */
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
/** Resumes execution after a drain. */
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
/**
* Commit has reached a safe point to drain a thread.
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
- virtual void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
+ virtual void wakeup(ThreadID tid) override;
/** Gets a free thread id. Use if thread ids change across system. */
ThreadID getFreeTid();
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
-#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
#include <list>
#include <memory>
#include <set>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
#include "debug/MemDepUnit.hh"
/** Moves an entry to the ready list. */
inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
- typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
+ typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
typedef typename MemDepHash::iterator MemDepHashIt;
profilePC = 3;
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ void serialize(CheckpointOut &cp) const override
{
ThreadState::serialize(cp);
// Use the ThreadContext serialization helper to serialize the
::serialize(*tc, cp);
}
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ void unserialize(CheckpointIn &cp) override
{
// Prevent squashing - we don't have any instructions in
// flight that we need to squash since we just instantiated a
*/
void regStats();
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
/** Perform sanity checks after a drain. */
void drainSanityCheck() const;
public:
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
public:
BaseSimpleCPU(BaseSimpleCPUParams *params);
virtual ~BaseSimpleCPU();
- void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
+ void wakeup(ThreadID tid) override;
virtual void init();
public:
Trace::InstRecord *traceData;
virtual Counter totalInsts() const;
virtual Counter totalOps() const;
- void serializeThread(CheckpointOut &cp,
- ThreadID tid) const M5_ATTR_OVERRIDE;
- void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
};
{ }
/** Reads an integer register. */
- IntReg readIntRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+ IntReg readIntRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
return thread->readIntReg(si->srcRegIdx(idx));
}
/** Sets an integer register to a value. */
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
- M5_ATTR_OVERRIDE
+ void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
{
numIntRegWrites++;
thread->setIntReg(si->destRegIdx(idx), val);
}
/** Reads a floating point register of single register width. */
- FloatReg readFloatRegOperand(const StaticInst *si, int idx)
- M5_ATTR_OVERRIDE
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
{
numFpRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
/** Reads a floating point register in its binary format, instead
* of by value. */
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
- M5_ATTR_OVERRIDE
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
{
numFpRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
}
/** Sets a floating point register of single width to a value. */
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
- M5_ATTR_OVERRIDE
+ void setFloatRegOperand(const StaticInst *si, int idx,
+ FloatReg val) override
{
numFpRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
/** Sets the bits of a floating point register of single width
* to a binary value. */
void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val) M5_ATTR_OVERRIDE
+ FloatRegBits val) override
{
numFpRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatRegBits(reg_idx, val);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+ CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
return thread->readCCReg(reg_idx);
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
- M5_ATTR_OVERRIDE
+ void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
numCCRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
thread->setCCReg(reg_idx, val);
}
- MiscReg readMiscRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+ MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->readMiscReg(reg_idx);
}
- void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
- M5_ATTR_OVERRIDE
+ void setMiscRegOperand(const StaticInst *si, int idx,
+ const MiscReg &val) override
{
numIntRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
* Reads a miscellaneous register, handling any architectural
* side effects due to reading that register.
*/
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE
+ MiscReg readMiscReg(int misc_reg) override
{
numIntRegReads++;
return thread->readMiscReg(misc_reg);
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
- void setMiscReg(int misc_reg, const MiscReg &val) M5_ATTR_OVERRIDE
+ void setMiscReg(int misc_reg, const MiscReg &val) override
{
numIntRegWrites++;
thread->setMiscReg(misc_reg, val);
}
- PCState pcState() const M5_ATTR_OVERRIDE
+ PCState pcState() const override
{
return thread->pcState();
}
- void pcState(const PCState &val) M5_ATTR_OVERRIDE
+ void pcState(const PCState &val) override
{
thread->pcState(val);
}
*
* @note Only valid for memory ops.
*/
- void setEA(Addr EA) M5_ATTR_OVERRIDE
+ void setEA(Addr EA) override
{ panic("BaseSimpleCPU::setEA() not implemented\n"); }
/**
*
* @note Only valid for memory ops.
*/
- Addr getEA() const M5_ATTR_OVERRIDE
+ Addr getEA() const override
{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
Fault readMem(Addr addr, uint8_t *data, unsigned int size,
- unsigned int flags) M5_ATTR_OVERRIDE
+ unsigned int flags) override
{
return cpu->readMem(addr, data, size, flags);
}
Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
- unsigned int flags, uint64_t *res) M5_ATTR_OVERRIDE
+ unsigned int flags, uint64_t *res) override
{
return cpu->writeMem(data, size, addr, flags, res);
}
/**
* Sets the number of consecutive store conditional failures.
*/
- void setStCondFailures(unsigned int sc_failures) M5_ATTR_OVERRIDE
+ void setStCondFailures(unsigned int sc_failures) override
{
thread->setStCondFailures(sc_failures);
}
/**
* Returns the number of consecutive store conditional failures.
*/
- unsigned int readStCondFailures() const M5_ATTR_OVERRIDE
+ unsigned int readStCondFailures() const override
{
return thread->readStCondFailures();
}
/**
* Executes a syscall specified by the callnum.
*/
- void syscall(int64_t callnum) M5_ATTR_OVERRIDE
+ void syscall(int64_t callnum) override
{
if (FullSystem)
panic("Syscall emulation isn't available in FS mode.");
}
/** Returns a pointer to the ThreadContext. */
- ThreadContext *tcBase() M5_ATTR_OVERRIDE
+ ThreadContext *tcBase() override
{
return thread->getTC();
}
* Somewhat Alpha-specific function that handles returning from an
* error or interrupt.
*/
- Fault hwrei() M5_ATTR_OVERRIDE
+ Fault hwrei() override
{
return thread->hwrei();
}
* Check for special simulator handling of specific PAL calls. If
* return value is false, actual PAL call will be suppressed.
*/
- bool simPalCheck(int palFunc) M5_ATTR_OVERRIDE
+ bool simPalCheck(int palFunc) override
{
return thread->simPalCheck(palFunc);
}
- bool readPredicate() M5_ATTR_OVERRIDE
+ bool readPredicate() override
{
return thread->readPredicate();
}
- void setPredicate(bool val) M5_ATTR_OVERRIDE
+ void setPredicate(bool val) override
{
thread->setPredicate(val);
/**
* Invalidate a page in the DTLB <i>and</i> ITLB.
*/
- void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE
+ void demapPage(Addr vaddr, uint64_t asn) override
{
thread->demapPage(vaddr, asn);
}
- void armMonitor(Addr address) M5_ATTR_OVERRIDE
+ void armMonitor(Addr address) override
{
cpu->armMonitor(thread->threadId(), address);
}
- bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE
+ bool mwait(PacketPtr pkt) override
{
return cpu->mwait(thread->threadId(), pkt);
}
- void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE
+ void mwaitAtomic(ThreadContext *tc) override
{
cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
}
- AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE
+ AddressMonitor *getAddrMonitor() override
{
return cpu->getCpuAddrMonitor(thread->threadId());
}
#if THE_ISA == MIPS_ISA
MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
- M5_ATTR_OVERRIDE
+ override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}
void setRegOtherThread(int regIdx, MiscReg val,
- ThreadID tid = InvalidThreadID) M5_ATTR_OVERRIDE
+ ThreadID tid = InvalidThreadID) override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
#ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__
#define __CPU_SIMPLE_PROBES_SIMPOINT_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "cpu/simple_thread.hh"
#include "params/SimPoint.hh"
#include "sim/probe/probe.hh"
typedef std::pair<Addr, Addr> BasicBlockRange;
/** Overload hash function for BasicBlockRange type */
-__hash_namespace_begin
+namespace std {
template <>
struct hash<BasicBlockRange>
{
return hash<Addr>()(bb.first + bb.second);
}
};
-__hash_namespace_end
+}
class SimPoint : public ProbeListenerObject
{
};
/** Hash table containing all previously seen basic blocks */
- m5::hash_map<BasicBlockRange, BBInfo> bbMap;
+ std::unordered_map<BasicBlockRange, BBInfo> bbMap;
/** Currently executing basic block */
BasicBlockRange currentBBV;
/** inst count in current basic block */
public:
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
void copyState(ThreadContext *oldContext);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void startup();
/***************************************************************
{
DPRINTF(RubyTest, "Looking for check by address: %s", address);
- m5::hash_map<Addr, Check*>::iterator i = m_lookup_map.find(address);
+ auto i = m_lookup_map.find(address);
if (i == m_lookup_map.end())
return NULL;
#define __CPU_RUBYTEST_CHECKTABLE_HH__
#include <iostream>
+#include <unordered_map>
#include <vector>
-#include "base/hashmap.hh"
#include "mem/ruby/common/Address.hh"
class Check;
CheckTable& operator=(const CheckTable& obj);
std::vector<Check*> m_check_vector;
-
m5::hash_map<Addr, Check*> m_lookup_map;
+
std::unordered_map<Addr, Check*> m_lookup_map;
int m_num_writers;
int m_num_readers;
#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "base/statistics.hh"
#include "cpu/testers/traffic_gen/generators.hh"
#include "mem/mem_object.hh"
uint32_t currState;
/** Map of generator states */
- m5::hash_map<uint32_t, BaseGen*> states;
+ std::unordered_map<uint32_t, BaseGen*> states;
/** Master port specialisation for the traffic generator */
class TrafficGenPort : public MasterPort
void initState();
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Register statistics */
void regStats();
virtual ~ThreadState();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) override;
int cpuId() const { return baseCpu->cpuId(); }
protected:
struct Access : public AlphaAccess, public Serializable
{
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
union {
/**
* standard serialization routines for checkpointing
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_ALPHA_BACKDOOR_HH__
*/
virtual Addr calcPciMemAddr(Addr addr);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_TSUNAMI_HH__
*/
void reqIPI(uint64_t ipreq);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __TSUNAMI_CCHIP_HH__
*/
void clearPIC(uint8_t bitvector);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Start running.
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __TSUNAMI_PCHIP_HH__
*/
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void startup();
void init();
~FlashDevice();
/** Checkpoint functions*/
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
void checkDrain();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
/** Defines the possible actions to the flash*/
void setKernelControl(uint32_t val) { _regCntkctl = val; }
uint32_t getKernelControl() { return _regCntkctl; }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
// Disable copying
/// Returns the value of the counter which this timer relies on.
uint64_t value() const;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
// Disable copying
public:
GenericTimer(GenericTimerParams *p);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public:
void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
: parent(_parent), cpu(_cpu) {}
- void setMiscReg(int misc_reg, ArmISA::MiscReg val) M5_ATTR_OVERRIDE {
+ void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
parent.setMiscReg(misc_reg, cpu, val);
}
- ArmISA::MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE {
+ ArmISA::MiscReg readMiscReg(int misc_reg) override {
return parent.readMiscReg(misc_reg, cpu);
}
public:
GenericTimerMem(GenericTimerMemParams *p);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public: // PioDevice
- AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; }
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ AddrRangeList getAddrRanges() const override { return addrRanges; }
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
protected:
uint64_t ctrlRead(Addr addr, size_t size) const;
void driveIrqEn(bool state);
/** @} */
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
protected:
/** Handle a read to the distributor poriton of the GIC
virtual ~NoMaliGpu();
public: /* Checkpointing */
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public: /* IO device interfaces */
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
- AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE;
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
+ AddrRangeList getAddrRanges() const override;
private:
/**
HDLcd(const HDLcdParams *p);
~HDLcd();
- void regStats() M5_ATTR_OVERRIDE;
+ void regStats() override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
public: // IO device interface
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
- AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; }
+ AddrRangeList getAddrRanges() const override { return addrRanges; }
protected: // Parameters
VncInput *vnc;
void dumpSettings();
protected:
- bool nextPixel(Pixel &p) M5_ATTR_OVERRIDE { return parent.pxlNext(p); }
+ bool nextPixel(Pixel &p) override { return parent.pxlNext(p); }
- void onVSyncBegin() M5_ATTR_OVERRIDE { return parent.pxlVSyncBegin(); }
- void onVSyncEnd() M5_ATTR_OVERRIDE { return parent.pxlVSyncEnd(); }
+ void onVSyncBegin() override { return parent.pxlVSyncBegin(); }
+ void onVSyncEnd() override { return parent.pxlVSyncEnd(); }
- void onUnderrun(unsigned x, unsigned y) M5_ATTR_OVERRIDE {
+ void onUnderrun(unsigned x, unsigned y) override {
parent.pxlUnderrun();
}
- void onFrameDone() M5_ATTR_OVERRIDE { parent.pxlFrameDone(); }
+ void onFrameDone() override { parent.pxlFrameDone(); }
protected:
HDLcd &parent;
void abortFrame();
void dumpSettings();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
protected:
- void onEndOfBlock() M5_ATTR_OVERRIDE;
- void onIdle() M5_ATTR_OVERRIDE;
+ void onEndOfBlock() override;
+ void onIdle() override;
HDLcd &parent;
const size_t lineSize;
virtual void mouseAt(uint16_t x, uint16_t y, uint8_t buttons);
virtual void keyPress(uint32_t key, bool down);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_ARM_PL050_HH__
public:
Pl011(const Pl011Params *p);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public: // PioDevice
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
public: // Uart
- void dataAvailable() M5_ATTR_OVERRIDE;
+ void dataAvailable() override;
protected: // Interrupt handling
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Determine the address ranges that this device responds to.
*/
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
* @param pkt The memory request.
* @param data Where to put the data.
*/
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick read(PacketPtr pkt) override;
/**
* All writes are simply ignored.
* @param pkt The memory request.
* @param data the data
*/
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick write(PacketPtr pkt) override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public:
void registerDevice(DeviceFunc func, uint8_t site, uint8_t pos,
RealViewOsc(RealViewOscParams *p);
virtual ~RealViewOsc() {};
- void startup() M5_ATTR_OVERRIDE;
+ void startup() override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public: // RealViewCtrl::Device interface
- uint32_t read() const M5_ATTR_OVERRIDE;
- void write(uint32_t freq) M5_ATTR_OVERRIDE;
+ uint32_t read() const override;
+ void write(uint32_t freq) override;
protected:
void clockPeriod(Tick clock_period);
/** Handle write for a single timer */
void write(PacketPtr pkt, Addr daddr);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
friend class CpuLocalTimer;
};
*/
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
/** Handle write for a single timer */
void write(PacketPtr pkt, Addr daddr);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
/** Pointer to the GIC for causing an interrupt */
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
UFSHostDevice(const UFSHostDeviceParams* p);
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
void checkDrain();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
/**
uint8_t VMBP;
uint8_t VMPriMask;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
struct std::array<vcpuIntData, VGIC_CPU_MAX> vcpuData;
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
Tick readVCpu(PacketPtr pkt);
void channelRead(PacketPtr pkt, Addr daddr, int size);
void channelWrite(PacketPtr pkt, Addr daddr, int size);
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
void fetchDescriptor(Addr address);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif //__DEV_COPY_ENGINE_HH__
uint32_t attnStatus; // Read clears
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ void serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(chanCount);
SERIALIZE_SCALAR(xferCap);
SERIALIZE_SCALAR(attnStatus);
}
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ void unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(chanCount);
UNSERIALIZE_SCALAR(xferCap);
};
CHANERR error;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ void serialize(CheckpointOut &cp) const override
{
paramOut(cp, "ctrl", ctrl._data);
paramOut(cp, "status", status._data);
paramOut(cp, "error", error._data);
}
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ void unserialize(CheckpointIn &cp) override
{
paramIn(cp, "ctrl", ctrl._data);
paramIn(cp, "status", status._data);
#define __DISK_IMAGE_HH__
#include <fstream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "params/CowDiskImage.hh"
#include "params/DiskImage.hh"
#include "params/RawDiskImage.hh"
struct Sector {
uint8_t data[SectorSize];
};
- typedef m5::hash_map<uint64_t, Sector *> SectorTable;
+ typedef std::unordered_map<uint64_t, Sector *> SectorTable;
protected:
std::string filename;
void save(const std::string &file) const;
void writeback();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
virtual std::streampos size() const;
bool dmaPending() const { return pendingCount > 0; }
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
};
class DmaDevice : public PioDevice
~DmaReadFifo();
public: // Serializable
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public: // Drainable
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
public: // FIFO access
/**
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
virtual bool recvPacket(EthPacketPtr packet);
virtual void sendDone();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
class EtherTapInt : public EtherInt
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif //__DEV_I2CBUS
void reset();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
virtual bool hasOutstandingEvents() {
return wbEvent.scheduled() || fetchEvent.scheduled();
virtual bool hasOutstandingEvents();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
friend class RxDescCache;
}
EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
friend class TxDescCache;
bool ethRxPkt(EthPacketPtr packet);
void ethTxDone();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
};
uint32_t sw_fw_sync;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ void serialize(CheckpointOut &cp) const override
{
paramOut(cp, "ctrl", ctrl._data);
paramOut(cp, "sts", sts._data);
SERIALIZE_SCALAR(sw_fw_sync);
}
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ void unserialize(CheckpointIn &cp) override
{
paramIn(cp, "ctrl", ctrl._data);
paramIn(cp, "sts", sts._data);
Tick read(PacketPtr pkt);
Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __IDE_CTRL_HH_
inline Addr pciToDma(Addr pciAddr);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
M5_DUMMY_RETURN
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_MALTA_HH__
*/
void reqIPI(uint64_t ipreq);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __MALTA_CCHIP_HH__
/** Clear an Interrupt to the CPU */
void clearIntr(uint8_t interrupt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Start running.
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __TSUNAMI_PCHIP_HH__
}
virtual EtherInt *getEthPort(const std::string &if_name,
- int idx) M5_ATTR_OVERRIDE;
+ int idx) override;
- void memWriteback() M5_ATTR_OVERRIDE;
- void init() M5_ATTR_OVERRIDE;
- void startup() M5_ATTR_OVERRIDE;
+ void memWriteback() override;
+ void init() override;
+ void startup() override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_MULTIETHERLINK_HH__
* This is a global event so process() will be called by each
* simulation threads. (See further comments in the .cc file.)
*/
- void process() M5_ATTR_OVERRIDE;
+ void process() override;
/**
* Schedule periodic sync when resuming from a checkpoint.
*/
*/
void initRandom();
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
/**
* Callback when draining is complete.
bool recvPacket(EthPacketPtr packet);
void transferDone();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
};
/*
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
/**
* Reconstruct the state of this object from a checkpoint.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) override;
virtual BaseSlavePort &getSlavePort(const std::string &if_name,
unsigned hbp, unsigned h_sync, unsigned hfp,
unsigned vbp, unsigned v_sync, unsigned vfp);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** How many pixel clocks are required for one line? */
Cycles cyclesPerLine() const {
BasePixelPump(EventManager &em, ClockDomain &pxl_clk, unsigned pixel_chunk);
virtual ~BasePixelPump();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public: // Public API
/** Starting pushing pixels using the supplied display timings. */
public:
PixelEvent(const char *name, BasePixelPump *parent, CallbackType func);
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- const std::string name() const M5_ATTR_OVERRIDE { return _name; }
- void process() M5_ATTR_OVERRIDE {
+ const std::string name() const override { return _name; }
+ void process() override {
(parent.*func)();
}
* Serialization stuff
*/
public:
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Construction/Destruction/Parameters
public:
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- virtual void drainResume() M5_ATTR_OVERRIDE;
+ virtual void drainResume() override;
void prepareIO(ContextID cpu, int index);
void prepareRead(ContextID cpu, int index);
* Serialization stuff
*/
public:
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
public:
Device(const Params *p);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_BADDEV_HH__
AddrRangeList getAddrRanges() const;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif //__DEV_SPARC_IOB_HH__
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
};
#endif //__DEV_SPARC_MM_DISK_HH__
virtual void
sendRaw(void *buf, unsigned length,
- const MultiHeaderPkt::AddressType dest_addr=nullptr)
- M5_ATTR_OVERRIDE
+ const MultiHeaderPkt::AddressType dest_addr=nullptr) override
{
sendTCP(sock, buf, length);
}
- virtual bool recvRaw(void *buf, unsigned length) M5_ATTR_OVERRIDE
+ virtual bool recvRaw(void *buf, unsigned length) override
{
return recvTCP(sock, buf, length);
}
virtual void syncRaw(MultiHeaderPkt::MsgType sync_req,
- Tick sync_tick) M5_ATTR_OVERRIDE;
+ Tick sync_tick) override;
public:
/**
unsigned multi_rank, Tick sync_start, Tick sync_repeat,
EventManager *em);
- ~TCPIface() M5_ATTR_OVERRIDE;
+ ~TCPIface() override;
};
#endif
*/
virtual bool intStatus() { return status ? true : false; }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __TSUNAMI_UART_HH__
/** @{
* @name Checkpointing Interface
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** @{
* @name Low-level Device Interface
/** @{
* @name SimObject Interfaces
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** @} */
VirtIO9PProxy(Params *params);
virtual ~VirtIO9PProxy();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
protected:
void recvTMsg(const P9MsgHeader &header, const uint8_t *data, size_t size);
virtual void startup();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace X86ISA
bool processData(uint8_t data);
- void serialize(const std::string &base,
- CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(const std::string &base,
- CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(const std::string &base, CheckpointOut &cp) const override;
+ void unserialize(const std::string &base, CheckpointIn &cp) override;
};
class PS2Keyboard : public PS2Device
Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace X86ISA
BaseMasterPort &getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID);
- Tick recvResponse(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick recvResponse(PacketPtr pkt) override;
void signalInterrupt(int line);
void raiseInterruptPin(int number);
void lowerInterruptPin(int number);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace X86ISA
Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace X86ISA
pit.writeControl(val);
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
virtual void startup();
void lowerInterruptPin(int number);
int getVector();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace X86ISA
Tick write(PacketPtr pkt);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace X86ISA
void swpipl(int ipl);
public:
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace Kernel
/** serialize the state of the caches
* We currently don't support checkpointing cache state, so this panics.
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
/**
CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
: cache(_cache), visitor(_visitor) {}
- bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
+ bool operator()(CacheBlk &blk) override {
return (cache.*visitor)(blk);
}
CacheBlkIsDirtyVisitor()
: _isDirty(false) {}
- bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
+ bool operator()(CacheBlk &blk) override {
if (blk.isDirty()) {
_isDirty = true;
return false;
return readyList.empty() ? MaxTick : readyList.front()->readyTime;
}
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
};
#endif //__MEM_CACHE_MSHR_QUEUE_HH__
#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
#define __MEM_CACHE_PREFETCH_STRIDE_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "mem/cache/prefetch/queued.hh"
#include "params/StridePrefetcher.hh"
const int pcTableAssoc;
const int pcTableSets;
const std::string _name;
- m5::hash_map<int, StrideEntry**> entries;
+ std::unordered_map<int, StrideEntry**> entries;
StrideEntry** allocateNewContext(int context);
};
*
* \param visitor Visitor to call on each block.
*/
- void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE {
+ void forEachBlk(CacheBlkVisitor &visitor) override {
for (unsigned i = 0; i < numSets * assoc; ++i) {
if (!visitor(blks[i]))
return;
#define __MEM_CACHE_TAGS_FA_LRU_HH__
#include <list>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/cache/tags/base.hh"
#include "mem/cache/blk.hh"
#include "mem/packet.hh"
FALRUBlk *tail;
/** Hash table type mapping addresses to cache block pointers. */
- typedef
m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
+ typedef
std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t;
/** Iterator into the address hash table. */
typedef hash_t::const_iterator tagIterator;
*
* \param visitor Visitor to call on each block.
*/
- void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE {
+ void forEachBlk(CacheBlkVisitor &visitor) override {
for (int i = 0; i < numBlocks; i++) {
if (!visitor(blks[i]))
return;
* responses from so we can determine which snoop responses we
* generated and which ones were merely forwarded.
*/
- m5::hash_set<RequestPtr> outstandingSnoop;
+ std::unordered_set<RequestPtr> outstandingSnoop;
/**
* Keep a pointer to the system to be allow to querying memory system
*/
CommMonitor(Params* params);
- void init() M5_ATTR_OVERRIDE;
- void regStats() M5_ATTR_OVERRIDE;
- void startup() M5_ATTR_OVERRIDE;
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void init() override;
+ void regStats() override;
+ void startup() override;
+ void regProbePoints() override;
public: // MemObject interfaces
BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID) M5_ATTR_OVERRIDE;
+ PortID idx = InvalidPortID) override;
BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID) M5_ATTR_OVERRIDE;
+ PortID idx = InvalidPortID) override;
private:
DRAMCtrl(const DRAMCtrlParams* p);
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
PortID idx = InvalidPortID);
- virtual void init() M5_ATTR_OVERRIDE;
- virtual void startup() M5_ATTR_OVERRIDE;
- virtual void drainResume() M5_ATTR_OVERRIDE;
+ virtual void init() override;
+ virtual void startup() override;
+ virtual void drainResume() override;
protected:
#define __MEM_DRAMSIM2_HH__
#include <queue>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/abstract_mem.hh"
#include "mem/dramsim2_wrapper.hh"
#include "mem/qport.hh"
* done so that we can return the right packet on completion from
* DRAMSim.
*/
-
m5::hash_map<Addr, std::queue<PacketPtr> > outstandingReads;
-
m5::hash_map<Addr, std::queue<PacketPtr> > outstandingWrites;
+
std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
+
std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
/**
* Count the number of outstanding transactions so that we can
*/
void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
PortID idx = InvalidPortID);
#include <list>
#include <map>
#include <string>
+#include <unordered_map>
#include <vector>
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/MemChecker.hh"
* Map of Serial --> Transaction of all writes in cluster; contains
* all, in-flight or already completed.
*/
- m5::hash_map<Serial, Transaction> writes;
+ std::unordered_map<Serial, Transaction> writes;
private:
Tick completeMax;
*
* Access via getByteTracker()!
*/
-
m5::hash_map<Addr, ByteTracker> byte_trackers;
+
std::unordered_map<Addr, ByteTracker> byte_trackers;
};
inline MemChecker::Serial
void unmap(Addr vaddr, int64_t size);
bool isUnmapped(Addr vaddr, int64_t size);
bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
*/
void retry();
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
};
class ReqPacketQueue : public PacketQueue
#define __MEM_PAGE_TABLE_HH__
#include <string>
+#include <unordered_map>
#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "mem/request.hh"
class FuncPageTable : public PageTableBase
{
private:
- typedef
m5::hash_map<Addr, TheISA::TlbEntry> PTable;
+ typedef
std::unordered_map<Addr, TheISA::TlbEntry> PTable;
typedef PTable::iterator PTableItr;
PTable pTable;
*/
bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
/**
*
* @param os stream to serialize to
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
/**
* Serialize a specific store.
* serialization, this action is independent of how the address
* ranges are mapped to logical memories in the guest system.
*/
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) override;
/**
* Unserialize a specific backing store, identified by a section.
public:
BaseMemProbe(BaseMemProbeParams *params);
- void regProbeListeners() M5_ATTR_OVERRIDE;
+ void regProbeListeners() override;
protected:
/**
: ProbeListenerArgBase(pm, name),
parent(_parent) {}
- void notify(const ProbePoints::PacketInfo &pkt_info) M5_ATTR_OVERRIDE {
+ void notify(const ProbePoints::PacketInfo &pkt_info) override {
parent.handleRequest(pkt_info);
}
MemTraceProbe(MemTraceProbeParams *params);
protected:
- void handleRequest(const ProbePoints::PacketInfo &pkt_info) \
- M5_ATTR_OVERRIDE;
+ void handleRequest(const ProbePoints::PacketInfo &pkt_info) override;
/**
* Callback to flush and close all open output streams on exit. If
public:
StackDistProbe(StackDistProbeParams *params);
- void regStats() M5_ATTR_OVERRIDE;
+ void regStats() override;
protected:
- void handleRequest(const ProbePoints::PacketInfo &pkt_info) \
- M5_ATTR_OVERRIDE;
+ void handleRequest(const ProbePoints::PacketInfo &pkt_info) override;
protected:
// Cache line size to simulate
#include <iomanip>
#include <iostream>
-#include "base/hashmap.hh"
#include "base/types.hh"
const uint32_t ADDRESS_WIDTH = 64; // address width in bytes
#define __MEM_RUBY_PROFILER_ADDRESSPROFILER_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/common/Address.hh"
class AddressProfiler
{
public:
- typedef
m5::hash_map<Addr, AccessTraceForAddress> AddressMap;
+ typedef
std::unordered_map<Addr, AccessTraceForAddress> AddressMap;
public:
AddressProfiler(int num_of_sequencers, Profiler *profiler);
#include <vector>
#include "base/callback.hh"
-#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/PrefetchBit.hh"
{
assert(tag == makeLineAddress(tag));
// search the set for the tags
- m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
+ auto it = m_tag_index.find(tag);
if (it != m_tag_index.end())
if (m_cache[cacheSet][it->second]->m_Permission !=
AccessPermission_NotPresent)
{
assert(tag == makeLineAddress(tag));
// search the set for the tags
- m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
+ auto it = m_tag_index.find(tag);
if (it != m_tag_index.end())
return it->second;
return -1; // Not found
#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
#include <string>
+#include <unordered_map>
#include <vector>
-#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/CacheResourceType.hh"
// The first index is the # of cache lines.
// The second index is the the amount associativity.
-
m5::hash_map<Addr, int> m_tag_index;
+
std::unordered_map<Addr, int> m_tag_index;
std::vector<std::vector<AbstractCacheEntry*> > m_cache;
AbstractReplacementPolicy *m_replacementPolicy_ptr;
#ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
#define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/common/Address.hh"
PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
// Data Members (m_prefix)
-
m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
+
std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
};
template<class ENTRY>
#define __MEM_RUBY_STRUCTURES_PERSISTENTTABLE_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/MachineID.hh"
PersistentTable& operator=(const PersistentTable& obj);
// Data Members (m_prefix)
- typedef
m5::hash_map<Addr, PersistentTableEntry> AddressMap;
+ typedef
std::unordered_map<Addr, PersistentTableEntry> AddressMap;
AddressMap m_map;
};
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
PortID idx = InvalidPortID);
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
void wakeup();
void setDescription(const std::string& name) { m_description = name; };
#define __MEM_RUBY_STRUCTURES_TBETABLE_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/ruby/common/Address.hh"
template<class ENTRY>
TBETable& operator=(const TBETable& obj);
// Data Members (m_prefix)
-
m5::hash_map<Addr, ENTRY> m_map;
+
std::unordered_map<Addr, ENTRY> m_map;
private:
int m_number_of_TBEs;
#include <vector>
-#include "base/hashmap.hh"
#include "base/types.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
// A pointer to the controller is needed for atomic support.
void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
uint32_t getId() { return m_version; }
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
/* SLICC callback */
void dataCallback(const DataBlock & dblk);
//
void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
uint32_t getId() { return m_version; }
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
protected:
void ruby_hit_callback(PacketPtr pkt);
void resetStats();
void memWriteback();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+ void drainResume() override;
void process();
void startup();
bool functionalRead(Packet *ptr);
template <class KEY, class VALUE>
std::ostream &
-operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
+operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
{
- typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
- typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
+ auto i = map.begin();
+ auto end = map.end();
out << "[";
for (; i != end; ++i)
#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/SequencerRequestType.hh"
Cycles m_data_cache_hit_latency;
Cycles m_inst_cache_hit_latency;
- typedef
m5::hash_map<Addr, SequencerRequest*> RequestTable;
+ typedef
std::unordered_map<Addr, SequencerRequest*> RequestTable;
RequestTable m_writeRequestTable;
RequestTable m_readRequestTable;
// Global outstanding request count, across all request tables
SimpleMemory(const SimpleMemoryParams *p);
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
BaseSlavePort& getSlavePort(const std::string& if_name,
PortID idx = InvalidPortID);
#ifndef __MEM_SNOOP_FILTER_HH__
#define __MEM_SNOOP_FILTER_HH__
+#include <unordered_map>
#include <utility>
-#include "base/hashmap.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "mem/qport.hh"
/**
* HashMap of SnoopItems indexed by line address
*/
- typedef
m5::hash_map<Addr, SnoopItem> SnoopFilterCache;
+ typedef
std::unordered_map<Addr, SnoopItem> SnoopFilterCache;
/**
* Simple factory methods for standard return values.
#define __MEM_XBAR_HH__
#include <deque>
+#include <unordered_map>
#include "base/addr_range_map.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
#include "mem/mem_object.hh"
#include "mem/qport.hh"
*
* @return 1 if busy or waiting to retry, or 0 if idle
*/
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
/**
* Get the crossbar layer's name
* the underlying Request pointer inside the Packet stays
* constant.
*/
- m5::unordered_map<RequestPtr, PortID> routeTo;
+ std::unordered_map<RequestPtr, PortID> routeTo;
/** all contigous ranges seen by this crossbar */
AddrRangeList xbarRanges;
void startup();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
/**
*/
bool isEnabled() const { return enableHandler; }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
typedef std::map<DomainID, SrcClockDomain*> Domains;
#include <cassert>
#include <iostream>
#include <string>
+#include <unordered_map>
#include <vector>
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/smt.hh"
bool
EventQueue::debugVerify() const
{
- m5::hash_map<long, bool> map;
+ std::unordered_map<long, bool> map;
Tick time = 0;
short priority = 0;
virtual BaseGlobalEvent *globalEvent() { return NULL; }
#ifndef SWIG
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
#endif
};
fileOffset(0), filename(""), driver(NULL)
{ }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Check if the target file descriptor is in use.
virtual void initState();
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
public:
*/
bool map(Addr vaddr, Addr paddr, int size, bool cacheable = true);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
//
/** Schedule the timesync event at loadState() so that curTick is correct
*/
- void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void loadState(CheckpointIn &cp) override;
/** Schedule the timesync event at initState() when not unserializing
*/
void initState();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __SIM_ROOT_HH__
Globals()
: unserializedCurTick(0) {}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
Tick unserializedCurTick;
};
virtual const char *description() const;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
static Serializable *createForUnserialize(CheckpointIn &cp,
const std::string §ion);
};
* Provide a default implementation of the drain interface for
* objects that don't need draining.
*/
- DrainState drain() M5_ATTR_OVERRIDE { return DrainState::Drained; }
+ DrainState drain() override { return DrainState::Drained; }
/**
* Write back dirty buffers to memory using functional writes.
*/
virtual void memInvalidate() {};
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE {};
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE {};
+ void serialize(CheckpointOut &cp) const override {};
+ void unserialize(CheckpointIn &cp) override {};
/**
* Serialize all SimObjects in the system.
ContextID assigned = InvalidContextID);
void replaceThreadContext(ThreadContext *tc, ContextID context_id);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
public:
Counter totalNumInsts;
}
/** Checkpoint lastStopped */
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Action to call on the clock tick */
virtual void evaluate() = 0;
/** Pass on regStats, serialize etc. onto Ticked */
void regStats();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif /* __SIM_TICKED_OBJECT_HH__ */
void regStats();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
private:
typedef std::vector<double> Voltages;
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