radeonsi: skip drawing if the tess factor ring allocation fails

Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 900b70f804cc05d936a391976441dabb82e93dec..3fc0799c2b4e1f94187156de32219b0375c875e4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -277,7 +277,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
                              unsigned force_level);
 
 /* si_state_shader.c */
-void si_update_shaders(struct si_context *sctx);
+bool si_update_shaders(struct si_context *sctx);
 void si_init_shader_functions(struct si_context *sctx);
 
 /* si_state_draw.c */

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index b4c59f805e5adf04b0b9e0d79a1e0ef37f6e4dd6..6d8e0e509bf88102b17a1b5a119bc4c05fad5668 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -759,8 +759,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
        else
                sctx->current_rast_prim = info->mode;
 
-       si_update_shaders(sctx);
-       if (!si_upload_shader_descriptors(sctx))
+       if (!si_update_shaders(sctx) ||
+           !si_upload_shader_descriptors(sctx))
                return;
 
        if (info->indexed) {

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 1f1965f6a56eab24313563f0a9dcd81d3638c0e9..11b58e8b3ca699300eb0335f799896e276a12527 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1279,6 +1279,9 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
        sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
                                           PIPE_USAGE_DEFAULT,
                                           32768 * sctx->screen->b.info.max_se);
+       if (!sctx->tf_ring)
+               return;
+
        assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
 
        /* Append these registers to the init config state. */
@@ -1385,15 +1388,18 @@ static void si_update_so(struct si_context *sctx, struct si_shader_selector *sha
        sctx->b.streamout.stride_in_dw = shader->so.stride;
 }
 
-void si_update_shaders(struct si_context *sctx)
+bool si_update_shaders(struct si_context *sctx)
 {
        struct pipe_context *ctx = (struct pipe_context*)sctx;
        struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
 
        /* Update stages before GS. */
        if (sctx->tes_shader) {
-               if (!sctx->tf_ring)
+               if (!sctx->tf_ring) {
                        si_init_tess_factor_ring(sctx);
+                       if (!sctx->tf_ring)
+                               return false;
+               }
 
                /* VS as LS */
                si_shader_select(ctx, sctx->vs_shader);
@@ -1487,6 +1493,7 @@ void si_update_shaders(struct si_context *sctx)
                if (sctx->b.chip_class == SI)
                        si_mark_atom_dirty(sctx, &sctx->db_render_state);
        }
+       return true;
 }
 
 void si_init_shader_functions(struct si_context *sctx)