Tweak yosys script

diff --git a/gram/simulation/simsoc.ys b/gram/simulation/simsoc.ys
index ffec515a27b9bd0d46dc4639c506506fe9437c83..77e4c13b8d34c237075d425f84c0825ef5678965 100644 (file)
--- a/gram/simulation/simsoc.ys
+++ b/gram/simulation/simsoc.ys
@@ -2,21 +2,17 @@ read_ilang build_simsoc/top.il
 delete w:$verilog_initial_trigger
 proc_prune
 proc_clean
+proc_rmdead
 proc_init
 proc_arst
+proc_dlatch
 proc_dff
 proc_rmdead
 proc_mux
 proc_clean
 pmuxtree
 memory_collect
-extract_fa -v
-clean
-flatten \ub
-flatten \decoder
-flatten \arbiter
-flatten \sysclk
-opt -fine -full
+extract_fa
 clean
 opt
 clean