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diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 5bda4fa419d45b2aea97b247a1dd6adf5f2edf98..08c36e0d424eb436c89be7f32c805f3f0f441f5c 100644 (file)
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -51,6 +51,8 @@ full context save/restore (see SVSRR0).  It contains (and permits setting of):
   instruction unless this bit is set, in which case REMAP "persists".
   Reset (cleared) on use of the `setvl` instruction if used to
   alter VL or MVL.
+* Pack - if set then srcstep/substep VL/SUBVL loop-ordering is inverted.
+* UnPack - if set then dststep/substep VL/SUBVL loop-ordering is inverted.
 * hphint - Horizontal Parallelism Hint. Indicates that
   no Hazards exist between these elements. In Vertical First Mode
    hardware **MUST** perform this many elements in parallel
@@ -127,7 +129,9 @@ The format of the SVSTATE SPR is as follows:
 | 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
 | 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
 | 42:46 | SVme     | REMAP enable (RA-RT)  |
-| 47:t4 | rsvd     | reserved              |
+| 47:52 | rsvd     | reserved              |
+| 53    | pack     | PACK (srcstrp reorder)  |
+| 54    | unpack   | UNPACK (dststep order)  |
 | 55:61 | hphint   | Horizontal Hint       |
 | 62    | RMpst    | REMAP persistence     |
 | 63    | vfirst   | Vertical First mode   |