Do not treat $__ABC_FF_ as a user cell

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ce2f6e571f0d644c5bbca97b62158eb89a62c280..923ba3da8e30fac331b7f682a357b72c7ec70dad 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -222,15 +222,15 @@ struct XAigerWriter
 
                        log_assert(!holes_mode);
 
-                       // FIXME: Should short here, rather than provide $__ABC_FF_
-                       //        to ABC like a user cell
-                       //if (cell->type == "$__ABC_FF_")
-                       //{
-                       //      SigBit D = sigmap(cell->getPort("\\D").as_bit());
-                       //      SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
-                       //      alias_map[Q] = D;
-                       //      continue;
-                       //}
+                       if (cell->type == "$__ABC_FF_")
+                       {
+                               SigBit D = sigmap(cell->getPort("\\D").as_bit());
+                               SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
+                               unused_bits.erase(D);
+                               undriven_bits.erase(Q);
+                               alias_map[Q] = D;
+                               continue;
+                       }
 
                        RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
                        bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index e13cd0eef17827ab04669b6ac3fbc85e50d67d69..decf5a6aa5fc8826953d3de83b5b9fdd9eb2a3f7 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -512,26 +512,18 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        }
                }
 
-               // Remove all AND, NOT, and ABC box instances
-               // in preparation for stitching mapped_mod in
-               // Short $_FF_ cells used by ABC (FIXME)
                dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
-               std::vector<RTLIL::Cell*> abc_dff;
                for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
                        RTLIL::Cell* cell = it->second;
-                       if (cell->type.in("$_AND_", "$_NOT_")) {
+                       if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) {
                                it = module->cells_.erase(it);
                                continue;
                        }
-                       if (cell->type.in("$__ABC_FF_"))
-                               abc_dff.emplace_back(cell);
-                       else {
-                               RTLIL::Module* box_module = design->module(cell->type);
-                               if (box_module && box_module->attributes.count("\\abc_box_id")) {
-                                       erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));
-                                       it = module->cells_.erase(it);
-                                       continue;
-                               }
+                       RTLIL::Module* box_module = design->module(cell->type);
+                       if (box_module && box_module->attributes.count("\\abc_box_id")) {
+                               erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));
+                               it = module->cells_.erase(it);
+                               continue;
                        }
                        ++it;
                }
@@ -695,13 +687,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        }
                }
 
-               for (auto cell : abc_dff) {
-                       RTLIL::SigBit D = cell->getPort("\\D");
-                       RTLIL::SigBit Q = cell->getPort("\\Q");
-                       module->connect(Q, D);
-                       module->remove(cell);
-               }
-
                //log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
                log("ABC RESULTS:           input signals: %8d\n", in_wires);
                log("ABC RESULTS:          output signals: %8d\n", out_wires);