arch: cpu: Stop passing around misc registers by reference.

These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.

Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 32d1aff6515f213811a3a6a9189cf488175a650d..685ddd479f199536a6596f715ea30302dc8fcdeb 100644 (file)
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -114,7 +114,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
 }
 
 void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
 {
     switch (misc_reg) {
       case MISCREG_FPCR:
@@ -140,8 +140,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 }
 
 void
-ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
-                ThreadID tid)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
 {
     switch (misc_reg) {
       case MISCREG_FPCR:

diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 36e708450967b7b77b6baf7c65d527d57035b8ba..54e12022a8e46d7b46d1062f68e732eb7b82afe6 100644 (file)
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -77,10 +77,9 @@ namespace AlphaISA
         MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
 
-        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
-                                ThreadID tid = 0);
-        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
-                        ThreadID tid = 0);
+        void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
+        void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc,
+                        ThreadID tid=0);
 
         void
         clear()

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ba7c0950957f8b25dfb12e1e7f881ccd84c26796..6cbf8db9017f60d12e8c7a40aff8639d611c7d2c 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -710,7 +710,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
 }
 
 void
-ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)
+ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
 {
     assert(misc_reg < NumMiscRegs);
 
@@ -732,7 +732,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)
 }
 
 void
-ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
 {
 
     RegVal newVal = val;

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index c365a1bd0dd50bd8d8394f8eec2506e1272e2824..60c572833cc86215a8d77413ff6dcffaaebbaed5 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -430,8 +430,8 @@ namespace ArmISA
       public:
         RegVal readMiscRegNoEffect(int misc_reg) const;
         RegVal readMiscReg(int misc_reg, ThreadContext *tc);
-        void setMiscRegNoEffect(int misc_reg, const RegVal &val);
-        void setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc);
+        void setMiscRegNoEffect(int misc_reg, RegVal val);
+        void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
 
         RegId
         flattenRegId(const RegId& regId) const

diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index df70bacbb73aaa9ba210f839d9f835146788bcd7..6f109f76f2fdebbc0f4d4635a2ccb17d43fb5b06 100644 (file)
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -445,7 +445,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc,  ThreadID tid)
 }
 
 void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
 {
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
@@ -458,7 +458,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 }
 
 void
-ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setRegMask(int misc_reg, MiscReg val, ThreadID tid)
 {
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
@@ -473,8 +473,7 @@ ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
 // be overwritten. Make sure to handle those particular registers
 // with care!
 void
-ISA::setMiscReg(int misc_reg, const MiscReg &val,
-                    ThreadContext *tc, ThreadID tid)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
 {
     int reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
@@ -497,7 +496,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
  * (setRegWithEffect)
 */
 MiscReg
-ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
+ISA::filterCP0Write(int misc_reg, int reg_sel, MiscReg val)
 {
     MiscReg retVal = val;
 

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 885ca2ff73cadc1c47ba3fd05a584593deeef7f5..ffcb3f1dcdacf478e91023d649e88bb3d0bc77d1 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -94,14 +94,13 @@ namespace MipsISA
         MiscReg readMiscReg(int misc_reg,
                             ThreadContext *tc, ThreadID tid = 0);
 
-        MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
-        void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
-        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
-                                ThreadID tid = 0);
+        MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val);
+        void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0);
+        void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
 
         //template <class TC>
-        void setMiscReg(int misc_reg, const MiscReg &val,
-                        ThreadContext *tc, ThreadID tid = 0);
+        void setMiscReg(int misc_reg, MiscReg val,
+                        ThreadContext *tc, ThreadID tid=0);
 
         //////////////////////////////////////////////////////////
         //

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 9769f8fd1af7e10d01e89678c024fc9d92ba5335..4e9fdb00aa3d51fe8aca9e549b582487fa1b56d4 100644 (file)
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -76,13 +76,13 @@ class ISA : public SimObject
     }
 
     void
-    setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+    setMiscRegNoEffect(int misc_reg, MiscReg val)
     {
         fatal("Power does not currently have any misc regs defined\n");
     }
 
     void
-    setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+    setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
     {
         fatal("Power does not currently have any misc regs defined\n");
     }

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index d99a742207a2e44dc9d5dda57ad8a163a53bea66..0f184b88286b14743a3d6016a2a96d8fd77c3b04 100644 (file)
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -164,7 +164,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
 }
 
 void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val)
 {
     if (misc_reg > NumMiscRegs || misc_reg < 0) {
         // Illegal CSR
@@ -175,7 +175,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 }
 
 void
-ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
 {
     if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
         // Ignore writes to HPM counters for now
@@ -200,4 +200,4 @@ RiscvISA::ISA *
 RiscvISAParams::create()
 {
     return new RiscvISA::ISA(this);
-}
\ No newline at end of file
+}

diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index f96b07275d837bfaed7d8bc7b10d040d6f024726..2602f6dde75e13f7532cb4aacf2a57e63fec299e 100644 (file)
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -76,8 +76,8 @@ class ISA : public SimObject
 
     MiscReg readMiscRegNoEffect(int misc_reg) const;
     MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
-    void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
-    void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+    void setMiscRegNoEffect(int misc_reg, MiscReg val);
+    void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc);
 
     RegId flattenRegId(const RegId &regId) const { return regId; }
     int flattenIntIndex(int reg) const { return reg; }

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 82fee0d0048bd6427ecbe661bb7e5fd61e7b3bcf..9209ba3de801d4fa22a977bf0d9ccaca208a7580 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -116,7 +116,7 @@ class ISA : public SimObject
 
     // These need to check the int_dis field and if 0 then
     // set appropriate bit in softint and checkinterrutps on the cpu
-    void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
+    void  setFSReg(int miscReg, MiscReg val, ThreadContext *tc);
     MiscReg readFSReg(int miscReg, ThreadContext * tc);
 
     // Update interrupt state on softint or pil change
@@ -186,9 +186,8 @@ class ISA : public SimObject
     MiscReg readMiscRegNoEffect(int miscReg) const;
     MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
-    void setMiscRegNoEffect(int miscReg, const MiscReg val);
-    void setMiscReg(int miscReg, const MiscReg val,
-            ThreadContext *tc);
+    void setMiscRegNoEffect(int miscReg, MiscReg val);
+    void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
 
     RegId
     flattenRegId(const RegId& regId) const

diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index d8af29b918dd083152b2f05e348a37b9f15d2df7..1a248d34255f9d0daf1781b44bdd0f9798dd07d7 100644 (file)
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -88,7 +88,7 @@ getMiscRegName(RegIndex index)
 }
 
 void
-ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
+ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
 {
     BaseCPU *cpu = tc->getCpuPtr();
 

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 2c7e022bdf678c9430dca3360e1a51c56ce04b3a..4468689bd1a4d5a1d59fb9c38be8994f2531120b 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -417,7 +417,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
     void
-    setMiscRegNoEffect(int misc_reg, const RegVal &val)
+    setMiscRegNoEffect(int misc_reg, RegVal val)
     {
         DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
                 misc_reg);
@@ -426,7 +426,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
     void
-    setMiscReg(int misc_reg, const RegVal &val) override
+    setMiscReg(int misc_reg, RegVal val) override
     {
         DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
                 misc_reg);
@@ -443,8 +443,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
     void
-    setMiscRegOperand(const StaticInst *si, int idx,
-                      const RegVal &val) override
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());

diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 854771fddf2b2539b37e8dea2cf9ac9fc1247e41..b5a2079eac34aec9568383802b4806dd04bdfcab 100644 (file)
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -348,7 +348,7 @@ class CheckerThreadContext : public ThreadContext
     { return actualTC->readMiscReg(misc_reg); }
 
     void
-    setMiscRegNoEffect(int misc_reg, const RegVal &val)
+    setMiscRegNoEffect(int misc_reg, RegVal val)
     {
         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -357,7 +357,7 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setMiscReg(int misc_reg, const RegVal &val)
+    setMiscReg(int misc_reg, RegVal val)
     {
         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
                          " and O3..\n", misc_reg);

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 0fe4a731a4adcbf54461376d284280d6d97eb49a..75f428b877a7e7155786908308a931b47c859114 100644 (file)
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -182,7 +182,7 @@ class ExecContext {
      */
     virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
     virtual void setMiscRegOperand(const StaticInst *si,
-                                   int idx, const RegVal &val) = 0;
+                                   int idx, RegVal val) = 0;
 
     /**
      * Reads a miscellaneous register, handling any architectural
@@ -194,7 +194,7 @@ class ExecContext {
      * Sets a miscellaneous register, handling any architectural
      * side effects due to writing that register.
      */
-    virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
+    virtual void setMiscReg(int misc_reg, RegVal val) = 0;
 
     /** @} */
 

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 9f8e9f7afeb951de16998da852e0e931bc2e313e..76d46e905416a8af56fd40bc5200a417b1f6a22b 100644 (file)
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -309,7 +309,7 @@ class ExecContext : public ::ExecContext
     }
 
     void
-    setMiscReg(int misc_reg, const RegVal &val) override
+    setMiscReg(int misc_reg, RegVal val) override
     {
         thread.setMiscReg(misc_reg, val);
     }
@@ -323,8 +323,7 @@ class ExecContext : public ::ExecContext
     }
 
     void
-    setMiscRegOperand(const StaticInst *si, int idx,
-                      const RegVal &val) override
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());
@@ -431,7 +430,7 @@ class ExecContext : public ::ExecContext
     }
 
     void
-    setRegOtherThread(const RegId &reg, const RegVal &val,
+    setRegOtherThread(const RegId &reg, RegVal val,
                       ThreadID tid=InvalidThreadID)
     {
         SimpleThread *other_thread = (tid == InvalidThreadID

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c65e509f95aa88cb718a3f67bd409369977fe7b3..600c89aa5bc3f7aab31479289c61d849f4603594 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1260,16 +1260,14 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
-        const RegVal &val, ThreadID tid)
+FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
 {
     this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
 }
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setMiscReg(int misc_reg,
-        const RegVal &val, ThreadID tid)
+FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
 {
     miscRegfileWrites++;
     this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 431eb0f2f90a42a4becba128b96567fd1064538c..90024bc84062d98a06d1fe462593443650af9855 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -390,12 +390,12 @@ class FullO3CPU : public BaseO3CPU
     RegVal readMiscReg(int misc_reg, ThreadID tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);
+    void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);
+    void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
 
     RegVal readIntReg(PhysRegIdPtr phys_reg);
 

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 9054b2089b1bda9fc4be841981e859bf32a77977..5bd0f8e4781779fb12432c9a6080dad89be90a4b 100644 (file)
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -146,7 +146,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * might have as defined by the architecture.
      */
     void
-    setMiscReg(int misc_reg, const RegVal &val)
+    setMiscReg(int misc_reg, RegVal val)
     {
         /** Writes to misc. registers are recorded and deferred until the
          * commit stage, when updateMiscRegs() is called. First, check if
@@ -182,7 +182,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * might have as defined by the architecture.
      */
     void
-    setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val)
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 510e96432807c381e2f4ea58a61c2ff000666285..c7493646954c06325a1e79577361e0a05ab72e1d 100644 (file)
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -331,11 +331,11 @@ class O3ThreadContext : public ThreadContext
     { return cpu->readMiscReg(misc_reg, thread->threadId()); }
 
     /** Sets a misc. register. */
-    virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val);
+    virtual void setMiscRegNoEffect(int misc_reg, RegVal val);
 
     /** Sets a misc. register, including any side-effects the
      * write might have as defined by the architecture. */
-    virtual void setMiscReg(int misc_reg, const RegVal &val);
+    virtual void setMiscReg(int misc_reg, RegVal val);
 
     virtual RegId flattenRegId(const RegId& regId) const;
 

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 086d2cfeb10712090e16a0fdd234df483fbc36c0..e1d771740e53e45051605d15491ecd6ca36dd7fc 100644 (file)
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -307,7 +307,7 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
 {
     cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
 
@@ -317,7 +317,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
 #endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val)
+O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
 {
     cpu->setMiscReg(misc_reg, val, thread->threadId());
 

diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index aa6ee8ba305929321c5f528d5775e8f6dee48e5b..7db7d20d98dd484837800b58951503905a463c61 100644 (file)
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -361,8 +361,7 @@ class SimpleExecContext : public ExecContext {
     }
 
     void
-    setMiscRegOperand(const StaticInst *si, int idx,
-                      const RegVal &val) override
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         numIntRegWrites++;
         const RegId& reg = si->destRegIdx(idx);
@@ -386,7 +385,7 @@ class SimpleExecContext : public ExecContext {
      * side effects due to writing that register.
      */
     void
-    setMiscReg(int misc_reg, const RegVal &val) override
+    setMiscReg(int misc_reg, RegVal val) override
     {
         numIntRegWrites++;
         thread->setMiscReg(misc_reg, val);

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 073f7ab2c4472ee1833e620152ebc3913a633555..211a4c89f64edf757538bd9099245102951f8d64 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -489,13 +489,13 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
+    setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
     {
         return isa->setMiscRegNoEffect(misc_reg, val);
     }
 
     void
-    setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
+    setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
     {
         return isa->setMiscReg(misc_reg, val, tc);
     }

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index db88227d9e2e56a8a345a4d570ca9ecf5cfff79d..cad073b4f5ce4b4c6277776cbd97ecc2a57aa4b5 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -278,9 +278,9 @@ class ThreadContext
 
     virtual RegVal readMiscReg(int misc_reg) = 0;
 
-    virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val) = 0;
+    virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
 
-    virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
+    virtual void setMiscReg(int misc_reg, RegVal val) = 0;
 
     virtual RegId flattenRegId(const RegId& regId) const = 0;
 
@@ -291,7 +291,7 @@ class ThreadContext
     }
 
     virtual void
-    setRegOtherThread(const RegId& misc_reg, const RegVal &val, ThreadID tid)
+    setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
     {
     }
 
@@ -541,10 +541,10 @@ class ProxyThreadContext : public ThreadContext
     RegVal readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    void setMiscRegNoEffect(int misc_reg, const RegVal &val)
+    void setMiscRegNoEffect(int misc_reg, RegVal val)
     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 
-    void setMiscReg(int misc_reg, const RegVal &val)
+    void setMiscReg(int misc_reg, RegVal val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
     RegId flattenRegId(const RegId& regId) const