def p_vars(self):
r = ""
for var in self.vars:
+ print(var.name)
r += "$var "
r += var.type
r += " "
def main():
myvcd = Vcd()
- myvcd.add(Var(1, "foo1", [0,1,0,1,0,1]))
- myvcd.add(Var(2, "foo2", [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
- myvcd.add(Var(3, "foo3"))
- myvcd.add(Var(4, "foo4"))
+ myvcd.add(Var("foo1", 1, [0,1,0,1,0,1]))
+ myvcd.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
+ myvcd.add(Var("foo3", 3))
+ myvcd.add(Var("foo4", 4))
ramp = [i%128 for i in range(1024)]
- myvcd.add(Var(16, "ramp", ramp))
+ myvcd.add(Var("ramp", 16, ramp))
print(myvcd)
if __name__ == '__main__':
from migen.fhdl.structure import *
-from migen.bus import csr
-from migen.bank import csrgen
from migen.bank.description import *
class MiIo(Module, AutoCSR):
def __init__(self, width):
self.width = width
- self.i = Signal(self.width)
- self.o = Signal(self.width)
+ self.i = Signal(width)
+ self.o = Signal(width)
- self._r_i = CSRStatus(self.width)
- self._r_o = CSRStorage(self.width)
+ self._r_i = CSRStatus(width)
+ self._r_o = CSRStorage(width)
self.sync +=[
self._r_i.status.eq(self.i),
from migen.fhdl.structure import *
-from migen.flow.actor import *
-from migen.flow.network import *
-from migen.bus import csr
-from migen.bank import description, csrgen
from migen.bank.description import *
from miscope.std import *
from miscope.storage import Recorder, RunLengthEncoder
class MiLa(Module, AutoCSR):
- def __init__(self, width, depth, ports, rle=False):
+ def __init__(self, width, depth, ports, with_rle=False):
self.width = width
self.sink = rec_dat(width)
self.comb += [
-
- trigger.sink.stb.eq(self.sink.stb),
- trigger.sink.dat.eq(self.sink.dat),
-
- recorder.trig_sink.stb.eq(trigger.source.stb),
- recorder.trig_sink.hit.eq(trigger.source.hit),
- trigger.source.ack.eq(recorder.trig_sink.ack),
-
- self.sink.ack.eq(1), #FIXME
+ self.sink.connect(trigger.sink),
+ trigger.source.connect(recorder.trig_sink)
]
- if rle:
- self.submodules.rle = RunLengthEncoder(width, 1024)
- self.comb +=[
- self.rle.sink.stb.eq(self.sink.stb),
- self.rle.sink.dat.eq(self.sink.dat),
-
- recorder.dat_sink.stb.eq(self.rle.source.stb),
- recorder.dat_sink.dat.eq(self.rle.source.dat),
- ]
- else:
- self.comb +=[
- recorder.dat_sink.stb.eq(self.sink.stb),
- recorder.dat_sink.dat.eq(self.sink.dat),
- ]
\ No newline at end of file
+ recorder_dat_source = self.sink
+ if with_rle:
+ self.submodules.rle = RunLengthEncoder(width)
+ self.comb += self.sink.connect(self.rle.sink)
+ recorder_dat_source = self.rle.source
+ self.comb += recorder_dat_source.connect(recorder.dat_sink)
def rec_dat(width):
layout = [
("stb", 1, DIR_M_TO_S),
- ("ack", 1, DIR_S_TO_M),
("dat", width, DIR_M_TO_S)
]
return Record(layout)
def rec_hit():
layout = [
("stb", 1, DIR_M_TO_S),
- ("ack", 1, DIR_S_TO_M),
("hit", 1, DIR_M_TO_S)
]
return Record(layout)
def rec_dat_hit(width):
layout = [
("stb", 1, DIR_M_TO_S),
- ("ack", 1, DIR_S_TO_M),
("hit", 1, DIR_M_TO_S),
("dat", width, DIR_M_TO_S)
]
from migen.fhdl.std import *
-from migen.flow.actor import *
-from migen.flow.network import *
-from migen.fhdl.specials import Memory
-from migen.bus import csr
-from migen.bank import description, csrgen
from migen.bank.description import *
from migen.genlib.fifo import SyncFIFO
from migen.genlib.fsm import FSM, NextState
from miscope.std import *
class RunLengthEncoder(Module, AutoCSR):
- def __init__(self, width, length):
+ def __init__(self, width, length=1024):
self.width = width
self.length = length
self.sink = rec_dat(width)
- self.source = rec_dat(width)
+ self.source = rec_dat(width)
self._r_enable = CSRStorage()
###
- enable = self._r_enable.storage
+ enable = self._r_enable.storage
stb_i = self.sink.stb
dat_i = self.sink.dat
- ack_i = self.sink.ack
# Register Input
stb_i_d = Signal()
dat_i_d = Signal(width)
- self.sync += [
+ self.sync += \
If(stb_i,
dat_i_d.eq(dat_i),
stb_i_d.eq(stb_i)
)
- ]
-
+
# Detect change
change = Signal()
- self.comb += [change.eq(stb_i & (~enable | (dat_i_d != dat_i)))]
+ self.comb += change.eq(stb_i & (~enable | (dat_i_d != dat_i)))
change_d = Signal()
change_rising = Signal()
rle_cnt = Signal(max=length)
rle_max = Signal()
- self.comb +=[If(rle_cnt == length, rle_max.eq(enable))]
+ self.comb += If(rle_cnt == length, rle_max.eq(enable))
- self.sync +=[
+ self.sync += \
If(change | rle_max,
rle_cnt.eq(0)
).Else(
rle_cnt.eq(rle_cnt + 1)
)
- ]
# Mux RLE word and data
stb_o = self.source.stb
dat_o = self.source.dat
- ack_o = self.source.ack
- self.comb +=[
+ self.comb += \
If(change_rising & ~rle_max,
stb_o.eq(1),
dat_o[width-1].eq(1),
dat_o.eq(dat_i_d)
).Else(
stb_o.eq(0),
- ),
- ack_i.eq(1) #FIXME
- ]
+ )
class Recorder(Module, AutoCSR):
def __init__(self, width, depth):
fsm.act("PRE_HIT_RECORDING",
fifo.we.eq(self.dat_sink.stb),
fifo.din.eq(self.dat_sink.dat),
- self.dat_sink.ack.eq(fifo.writable),
fifo.re.eq(fifo.level >= self._r_offset.storage),
fsm.act("POST_HIT_RECORDING",
fifo.we.eq(self.dat_sink.stb),
fifo.din.eq(self.dat_sink.dat),
- self.dat_sink.ack.eq(fifo.writable),
If(~fifo.writable | (fifo.level >= self._r_length.storage), NextState("IDLE"))
)
from migen.fhdl.std import *
-from migen.flow.actor import *
-from migen.flow.network import *
from migen.fhdl.specials import Memory
-from migen.bus import csr
-from migen.bank import description, csrgen
from migen.bank.description import *
from miscope.std import *
self.comb +=[
hit.eq((dat & mask) == trig),
- self.source.stb.eq(self.sink.stb),
- self.sink.ack.eq(self.sink.ack),
+ self.source.stb.eq(self.sink.stb)
]
class RangeDetector(Module, AutoCSR):
self._r_high = CSRStorage(width)
###
+
low = self._r_low.storage
high = self._r_high.storage
dat = self.sink.dat
self.comb +=[
hit.eq((dat >= low) & (dat <= high)),
- self.source.stb.eq(self.sink.stb),
- self.sink.ack.eq(self.sink.ack),
+ self.source.stb.eq(self.sink.stb)
]
self._r_both_mask = CSRStorage(width)
###
+
rising_mask = self._r_rising_mask.storage
falling_mask = self._r_falling_mask.storage
both_mask = self._r_both_mask.storage
falling_hit.eq(rising_mask & ~dat & dat_d),
both_hit.eq((both_mask & dat) != (both_mask & dat_d)),
hit.eq(rising_hit | falling_hit | both_hit),
- self.source.stb.eq(self.sink.stb),
- self.sink.ack.eq(self.sink.ack),
+ self.source.stb.eq(self.sink.stb)
]
class Sum(Module, AutoCSR):
self.comb +=[
self.source.stb.eq(optree("&", [sink.stb for sink in self.sinks])),
self.source.hit.eq(lut_port.dat_r),
- [sink.ack.eq(self.source.ack) for sink in self.sinks]
]
###
for i, port in enumerate(ports):
self.comb +=[
- port.sink.stb.eq(self.sink.stb),
- port.sink.dat.eq(self.sink.dat),
+ self.sink.connect(port.sink),
port.source.connect(self.sum.sinks[i])
]
\ No newline at end of file
projects / litex.git / commitdiff