cores/uart: add UARTCrossover

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index d9c0ea7eafaac432688980174a8c3f665c948aeb..a3d7122dd4c91a30c81fed3f2511b41c7d793af6 100644 (file)
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -264,3 +264,18 @@ class UARTMultiplexer(Module):
                 uarts[n].rx.eq(uart.rx)
             ]
         self.comb += Case(self.sel, cases)
+
+# UART Crossover -----------------------------------------------------------------------------------
+
+class UARTCrossover(UART):
+    """
+    UART crossover trough Wishbone bridge.
+
+    Creates a fully compatible UART that can be used by the CPU as a regular UART and adds a second
+    UART, cross-connected to the main one to allow terminal emulation over a Wishbone bridge.
+    """
+    def __init__(self, **kwargs):
+        assert kwargs.get("phy", None) == None
+        UART.__init__(self, **kwargs)
+        self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2)
+        self.comb += self.connect(self.xover)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 898ccb31c1fee780cf001f2028a4913b2780ba1a..6592e1a2770677e254ee63c3378957b48893499a 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -243,6 +243,8 @@ class SoCCore(Module):
                 self.submodules.uart = uart.UART()
                 if uart_name == "stub":
                     self.comb += uart.sink.ready.eq(1)
+            elif uart_name == "crossover":
+                self.submodules.uart = uart.UARTCrossover()
             else:
                 if uart_name == "jtag_atlantic":
                     from litex.soc.cores.jtag import JTAGAtlantic