return pcState().nextInstAddr();
}
+iris::MemorySpaceId
+ArmThreadContext::getBpSpaceId(Addr pc) const
+{
+ if (bpSpaceId == iris::IRIS_UINT64_MAX) {
+ for (auto &space: memorySpaces) {
+ if (space.canonicalMsn == CurrentMsn) {
+ bpSpaceId = space.spaceId;
+ break;
+ }
+ }
+ panic_if(bpSpaceId == iris::IRIS_UINT64_MAX,
+ "Unable to find address space for breakpoints.");
+ }
+ return bpSpaceId;
+}
+
uint64_t
ArmThreadContext::readIntReg(RegIndex reg_idx) const
{
{ 28, "V28" }, { 29, "V29" }, { 30, "V30" }, { 31, "V31" }
});
+iris::MemorySpaceId ArmThreadContext::bpSpaceId = iris::IRIS_UINT64_MAX;
+
} // namespace Iris
static IdxNameMap intReg32IdxNameMap;
static IdxNameMap intReg64IdxNameMap;
static IdxNameMap vecRegIdxNameMap;
+ static iris::MemorySpaceId bpSpaceId;
// Temporary holding places for the vector reg accessors to return.
// These are not updated live, only when requested.
ResourceIds intReg64Ids;
ResourceIds vecRegIds;
+ iris::MemorySpaceId getBpSpaceId(Addr pc) const override;
+
void setIntReg(RegIndex reg_idx, RegVal val) override;
RegVal readIntReg(RegIndex reg_idx) const override;
TheISA::ISA *
ThreadContext::installBp(BpInfoIt it)
{
BpId id;
- // Hard code address space 5 for now.
- call().breakpoint_set_code(_instId, id, it->second->pc, 5, 0, true);
+ Addr pc = it->second->pc;
+ auto space_id = getBpSpaceId(pc);
+ call().breakpoint_set_code(_instId, id, pc, space_id, 0, true);
it->second->id = id;
}
void uninstallBp(BpInfoIt it);
void delBp(BpInfoIt it);
+ virtual iris::MemorySpaceId getBpSpaceId(Addr pc) const = 0;
+
iris::IrisErrorCode instanceRegistryChanged(
uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,