Make hardware loads/stores serializing; they need to avoid certain out-of-order inter...

--HG--
extra : convert_revision : d83940af7d0e8efe891d574ac42c6d70d179e2b1

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 6df47ef7a07728741b726107b44a83cc18d50d8d..03c8cc29e7a0e07890e25f0a8a469081eda6a91a 100644 (file)
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -719,8 +719,10 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_st_quad();
         1: decode HW_LDST_QUAD {
             format HwLoad {
-                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
-                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
+                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
+                         L, IsSerializing, IsSerializeBefore);
+                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
+                         Q, IsSerializing, IsSerializeBefore);
             }
         }
     }
@@ -731,9 +733,9 @@ decode OPCODE default Unknown::unknown() {
             1: decode HW_LDST_COND {
                 0: decode HW_LDST_QUAD {
                     0: hw_st({{ EA = (Rb + disp) & ~3; }},
-                {{ Mem.ul = Ra<31:0>; }}, L);
+                {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
                     1: hw_st({{ EA = (Rb + disp) & ~7; }},
-                {{ Mem.uq = Ra.uq; }}, Q);
+                {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
                 }
 
                 1: FailUnimpl::hw_st_cond();