Remove _TECHMAP_CELLTYPE_ check since all $mul

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 25ff28ab5ef76a669728ee86f10077702bb76d48..8c6a836f8a621a1677aed2a12ef1fc169a431d58 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -61,8 +61,6 @@ module _80_mul (A, B, Y);
        input [B_WIDTH-1:0] B;\r
        output [Y_WIDTH-1:0] Y;\r
 \r
-       parameter _TECHMAP_CELLTYPE_ = "";\r
-\r
        generate\r
        if (0) begin end\r
 `ifdef DSP_A_MINWIDTH\r
@@ -77,10 +75,8 @@ module _80_mul (A, B, Y);
        else if (Y_WIDTH < `DSP_Y_MINWIDTH)\r
                wire _TECHMAP_FAIL_ = 1;\r
 `endif\r
-       else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)\r
-               wire _TECHMAP_FAIL_ = 1;\r
 `ifdef DSP_SIGNEDONLY\r
-       else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)\r
+       else if (!A_SIGNED)\r
                \$mul #(\r
                        .A_SIGNED(1),\r
                        .B_SIGNED(1),\r
@@ -93,7 +89,7 @@ module _80_mul (A, B, Y);
                        .Y(Y)\r
                );\r
 `endif\r
-       else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)\r
+       else if (A_WIDTH < B_WIDTH)\r
                \$mul #(\r
                        .A_SIGNED(B_SIGNED),\r
                        .B_SIGNED(A_SIGNED),\r