Ignore explicit assignments to constants in HDL code

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index f48101934744c498d5b30c6064a7031b792d894f..71248663ede0e1087b3773ea8df896a4f2a9c6a4 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1296,6 +1296,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                {
                        RTLIL::SigSpec left = children[0]->genRTLIL();
                        RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
+                       if (left.has_const()) {
+                               RTLIL::SigSpec new_left, new_right;
+                               for (int i = 0; i < GetSize(left); i++)
+                                       if (left[i].wire) {
+                                               new_left.append(left[i]);
+                                               new_right.append(right[i]);
+                                       }
+                               log_warning("Ignoring assignment to constant bits at %s:%d:\n"
+                                               "    old assignment: %s = %s\n    new assignment: %s = %s.\n",
+                                               filename.c_str(), linenum, log_signal(left), log_signal(right),
+                                               log_signal(new_left), log_signal(new_right));
+                               left = new_left;
+                               right = new_right;
+                       }
                        current_module->connect(RTLIL::SigSig(left, right));
                }
                break;