+2016-05-09 Prachi Godbole <prachi.godbole@imgtec.com>
+
+ * config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic)
+ (i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, i6400_fpu_store)
+ (i6400_fpu_long_pipe, i6400_fpu_logic_l, i6400_fpu_float_l)
+ (i6400_fpu_mult): New cpu units.
+ (i6400_msa_add_d, i6400_msa_int_add, i6400_msa_short_logic3)
+ (i6400_msa_short_logic2, i6400_msa_short_logic, i6400_msa_move)
+ (i6400_msa_cmp, i6400_msa_short_float2, i6400_msa_div_d)
+ (i6400_msa_div_w, i6400_msa_div_h, i6400_msa_div_b)
+ (i6400_msa_copy, i6400_msa_branch, i6400_fpu_msa_store)
+ (i6400_fpu_msa_load, i6400_fpu_msa_move, i6400_msa_long_logic1)
+ (i6400_msa_long_logic2, i6400_msa_mult, i6400_msa_long_float2)
+ (i6400_msa_long_float4, i6400_msa_long_float5)
+ (i6400_msa_long_float8, i6400_msa_fdiv_df)
+ (i6400_msa_fdiv_sf): New reservations.
+ * config/mips/p5600.md (p5600_fpu_intadd, p5600_fpu_cmp)
+ (p5600_fpu_float, p5600_fpu_logic_a, p5600_fpu_logic_b)
+ (p5600_fpu_div, p5600_fpu_logic, p5600_fpu_float_a)
+ (p5600_fpu_float_b, p5600_fpu_float_c, p5600_fpu_float_d)
+ (p5600_fpu_mult, p5600_fpu_fdiv, p5600_fpu_load): New cpu units.
+ (msa_short_int_add, msa_short_logic, msa_short_logic_move_v)
+ (msa_short_cmp, msa_short_float2, msa_short_logic3)
+ (msa_short_store4, msa_long_load, msa_short_store)
+ (msa_long_logic, msa_long_float2, msa_long_float4)
+ (msa_long_float5, msa_long_float8, msa_long_mult)
+ (msa_long_fdiv, msa_long_div): New reservations.
+
2016-05-09 Robert Suchanek <robert.suchanek@imgtec.com>
Sameera Deshpande <sameera.deshpande@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>
(define_cpu_unit "i6400_control, i6400_ctu, i6400_alu0" "i6400_int_pipe")
;; Short FPU pipeline.
-(define_cpu_unit "i6400_fpu_short" "i6400_fpu_short_pipe")
+(define_cpu_unit "i6400_fpu_short, i6400_fpu_intadd, i6400_fpu_logic,
+ i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float,
+ i6400_fpu_store" "i6400_fpu_short_pipe")
;; Long FPU pipeline.
-(define_cpu_unit "i6400_fpu_long, i6400_fpu_apu" "i6400_fpu_long_pipe")
+(define_cpu_unit "i6400_fpu_long, i6400_fpu_logic_l, i6400_fpu_float_l,
+ i6400_fpu_mult, i6400_fpu_apu" "i6400_fpu_long_pipe")
(define_reservation "i6400_control_ctu" "i6400_control, i6400_ctu")
(define_reservation "i6400_control_alu0" "i6400_control, i6400_alu0")
(define_reservation "i6400_agen_lsu" "i6400_agen, i6400_lsu")
(define_reservation "i6400_agen_alu1" "i6400_agen, i6400_alu1")
+;;
+;; FPU-MSA pipe
+;;
+
+;; Short pipe
+
+;; addv, subv
+(define_insn_reservation "i6400_msa_add_d" 1
+ (and (eq_attr "cpu" "i6400")
+ (and (eq_attr "mode" "!V2DI")
+ (eq_attr "alu_type" "simd_add")))
+ "i6400_fpu_short, i6400_fpu_intadd")
+
+;; add, hadd, sub, hsub, average, min, max, compare
+(define_insn_reservation "i6400_msa_int_add" 2
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_int_arith"))
+ "i6400_fpu_short, i6400_fpu_intadd")
+
+;; sat, pcnt
+(define_insn_reservation "i6400_msa_short_logic3" 3
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_sat,simd_pcnt"))
+ "i6400_fpu_short, i6400_fpu_logic")
+
+;; shifts, nloc, nlzc, bneg, bclr, shf
+(define_insn_reservation "i6400_msa_short_logic2" 2
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_shift,simd_shf,simd_bit"))
+ "i6400_fpu_short, i6400_fpu_logic")
+
+;; and, or, xor, ilv, pck, fill, splat
+(define_insn_reservation "i6400_msa_short_logic" 1
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_permute,simd_logic,simd_splat,simd_fill"))
+ "i6400_fpu_short, i6400_fpu_logic")
+
+;; move.v, ldi
+(define_insn_reservation "i6400_msa_move" 1
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_move"))
+ "i6400_fpu_short, i6400_fpu_logic")
+
+;; Float compare New: CMP.cond.fmt
+(define_insn_reservation "i6400_msa_cmp" 2
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_fcmp"))
+ "i6400_fpu_short, i6400_fpu_cmp")
+
+;; Float min, max, class
+(define_insn_reservation "i6400_msa_short_float2" 2
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_fminmax,simd_fclass"))
+ "i6400_fpu_short, i6400_fpu_float")
+
+;; div.d, mod.d (non-pipelined)
+(define_insn_reservation "i6400_msa_div_d" 36
+ (and (eq_attr "cpu" "i6400")
+ (and (eq_attr "mode" "V2DI")
+ (eq_attr "type" "simd_div")))
+ "i6400_fpu_short+i6400_fpu_div*36")
+
+;; div.w, mod.w (non-pipelined)
+(define_insn_reservation "i6400_msa_div_w" 20
+ (and (eq_attr "cpu" "i6400")
+ (and (eq_attr "mode" "V4SI")
+ (eq_attr "type" "simd_div")))
+ "i6400_fpu_short+i6400_fpu_div*20")
+
+;; div.h, mod.h (non-pipelined)
+(define_insn_reservation "i6400_msa_div_h" 12
+ (and (eq_attr "cpu" "i6400")
+ (and (eq_attr "mode" "V8HI")
+ (eq_attr "type" "simd_div")))
+ "i6400_fpu_short+i6400_fpu_div*12")
+
+;; div.b, mod.b (non-pipelined)
+(define_insn_reservation "i6400_msa_div_b" 8
+ (and (eq_attr "cpu" "i6400")
+ (and (eq_attr "mode" "V16QI")
+ (eq_attr "type" "simd_div")))
+ "i6400_fpu_short+i6400_fpu_div*8")
+
+;; Vector copy
+(define_insn_reservation "i6400_msa_copy" 1
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_copy"))
+ "i6400_fpu_short, i6400_fpu_store")
+
+;; Vector bz, bnz
+(define_insn_reservation "i6400_msa_branch" 1
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_branch"))
+ "i6400_control_ctu")
+
+;; Vector store
+(define_insn_reservation "i6400_fpu_msa_store" 1
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_store"))
+ "i6400_agen_lsu")
+
+;; Vector load
+(define_insn_reservation "i6400_fpu_msa_load" 3
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_load"))
+ "i6400_agen_lsu")
+
+;; cfcmsa, ctcmsa
+(define_insn_reservation "i6400_fpu_msa_move" 1
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_cmsa"))
+ "i6400_control_alu0 | i6400_agen_alu1")
+
+;; Long pipe
+
+;; bmz, bmnz, bsel, insert, insve
+(define_insn_reservation "i6400_msa_long_logic1" 1
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_bitmov,simd_insert"))
+ "i6400_fpu_long, i6400_fpu_logic_l")
+
+;; binsl, binsr, vshf, sld
+(define_insn_reservation "i6400_msa_long_logic2" 2
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_bitins,simd_sld"))
+ "i6400_fpu_long, i6400_fpu_logic_l")
+
+;; Vector mul, dotp, madd, msub
+(define_insn_reservation "i6400_msa_mult" 5
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_mul"))
+ "i6400_fpu_long, i6400_fpu_mult")
+
+;; Float flog2
+(define_insn_reservation "i6400_msa_long_float2" 2
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_flog2"))
+ "i6400_fpu_long, i6400_fpu_float_l")
+
+;; fadd, fsub
+(define_insn_reservation "i6400_msa_long_float4" 4
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_fadd,simd_fcvt"))
+ "i6400_fpu_long, i6400_fpu_float_l")
+
+;; fmul, fexp2
+(define_insn_reservation "i6400_msa_long_float5" 5
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_fmul,simd_fexp2"))
+ "i6400_fpu_long, i6400_fpu_float_l")
+
+;; fmadd, fmsub
+(define_insn_reservation "i6400_msa_long_float8" 8
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_fmadd"))
+ "i6400_fpu_long, i6400_fpu_float_l")
+
+;; fdiv.d
+(define_insn_reservation "i6400_msa_fdiv_df" 30
+ (and (eq_attr "cpu" "i6400")
+ (and (eq_attr "mode" "V2DF")
+ (eq_attr "type" "simd_fdiv")))
+ "i6400_fpu_long+i6400_fpu_float_l*30")
+
+;; fdiv.w
+(define_insn_reservation "i6400_msa_fdiv_sf" 22
+ (and (eq_attr "cpu" "i6400")
+ (eq_attr "type" "simd_fdiv"))
+ "i6400_fpu_long+i6400_fpu_float_l*22")
+
;;
;; FPU pipe
;;
(define_cpu_unit "p5600_fpu_short, p5600_fpu_long" "p5600_fpu_pipe")
;; Short FPU pipeline
-(define_cpu_unit "p5600_fpu_store" "p5600_fpu_pipe")
+(define_cpu_unit "p5600_fpu_intadd, p5600_fpu_cmp, p5600_fpu_float,
+ p5600_fpu_logic_a, p5600_fpu_logic_b, p5600_fpu_div,
+ p5600_fpu_store" "p5600_fpu_pipe")
;; Long FPU pipeline
-(define_cpu_unit "p5600_fpu_apu" "p5600_fpu_pipe")
+(define_cpu_unit "p5600_fpu_logic, p5600_fpu_float_a, p5600_fpu_float_b,
+ p5600_fpu_float_c, p5600_fpu_float_d" "p5600_fpu_pipe")
+(define_cpu_unit "p5600_fpu_mult, p5600_fpu_fdiv, p5600_fpu_load,
+ p5600_fpu_apu" "p5600_fpu_pipe")
(define_reservation "p5600_agq_al2" "p5600_agq, p5600_al2")
(define_reservation "p5600_agq_ctistd" "p5600_agq, p5600_ctistd")
(define_reservation "p5600_agq_ldsta" "p5600_agq, p5600_ldsta")
(define_reservation "p5600_alq_alu" "p5600_alq, p5600_alu")
+;;
+;; FPU-MSA pipe
+;;
+
+;; Arithmetic
+;; add, hadd, sub, hsub, average, min, max, compare
+(define_insn_reservation "msa_short_int_add" 2
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_int_arith"))
+ "p5600_fpu_short, p5600_fpu_intadd")
+
+;; Bitwise Instructions
+;; and, or, xor, bit-clear, leading-bits-count, shift, shuffle
+(define_insn_reservation "msa_short_logic" 2
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_shift,simd_bit,simd_splat,simd_fill,simd_shf,
+ simd_permute,simd_logic"))
+ "p5600_fpu_short, p5600_fpu_logic_a")
+
+;; move.v
+(define_insn_reservation "msa_short_logic_move_v" 2
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_move"))
+ "p5600_fpu_short, p5600_fpu_logic_a")
+
+;; Float compare
+(define_insn_reservation "msa_short_cmp" 2
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_fcmp"))
+ "p5600_fpu_short, p5600_fpu_cmp")
+
+;; Float exp2, min, max
+(define_insn_reservation "msa_short_float2" 2
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_fexp2,simd_fminmax"))
+ "p5600_fpu_short, p5600_fpu_float")
+
+;; Vector sat
+(define_insn_reservation "msa_short_logic3" 3
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_sat,simd_pcnt"))
+ "p5600_fpu_short, p5600_fpu_logic_a, p5600_fpu_logic_b")
+
+;; Vector copy, bz, bnz
+(define_insn_reservation "msa_short_store4" 4
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_copy,simd_branch,simd_cmsa"))
+ "p5600_fpu_short, p5600_fpu_store")
+
+;; Vector load
+(define_insn_reservation "msa_long_load" 10
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_load"))
+ "p5600_fpu_long, p5600_fpu_load")
+
+;; Vector store
+(define_insn_reservation "msa_short_store" 2
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_store"))
+ "p5600_fpu_short, p5600_fpu_store")
+
+;; binsl, binsr, insert, vshf, sld
+(define_insn_reservation "msa_long_logic" 2
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_bitins,simd_bitmov,simd_insert,simd_sld"))
+ "p5600_fpu_long, p5600_fpu_logic")
+
+;; Float fclass, flog2
+(define_insn_reservation "msa_long_float2" 2
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_fclass,simd_flog2"))
+ "p5600_fpu_long, p5600_fpu_float_a")
+
+;; fadd, fsub
+(define_insn_reservation "msa_long_float4" 4
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_fadd,simd_fcvt"))
+ "p5600_fpu_long, p5600_fpu_float_a, p5600_fpu_float_b")
+
+;; fmul
+(define_insn_reservation "msa_long_float5" 5
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_fmul"))
+ "p5600_fpu_long, p5600_fpu_float_a, p5600_fpu_float_b, p5600_fpu_float_c")
+
+;; fmadd, fmsub
+(define_insn_reservation "msa_long_float8" 8
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_fmadd"))
+ "p5600_fpu_long, p5600_fpu_float_a,
+ p5600_fpu_float_b, p5600_fpu_float_c, p5600_fpu_float_d")
+
+;; Vector mul, dotp, madd, msub
+(define_insn_reservation "msa_long_mult" 5
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_mul"))
+ "p5600_fpu_long, p5600_fpu_mult")
+
+;; fdiv, fmod (semi-pipelined)
+(define_insn_reservation "msa_long_fdiv" 10
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_fdiv"))
+ "p5600_fpu_long, nothing, nothing, p5600_fpu_fdiv*8")
+
+;; div, mod (non-pipelined)
+(define_insn_reservation "msa_long_div" 10
+ (and (eq_attr "cpu" "p5600")
+ (eq_attr "type" "simd_div"))
+ "p5600_fpu_long, p5600_fpu_div*9, p5600_fpu_div + p5600_fpu_logic_a")
+
;;
;; FPU pipe
;;
projects / gcc.git / commitdiff