Added "extract -map %<design_name>"

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index eff14ff01ea126ac9340e1b0e00e593148ac7047..06b0df2debe12c4967a83499ffa03624850c7a46 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -315,6 +315,10 @@ struct ExtractPass : public Pass {
                log("        use the modules in this file as reference. This option can be used\n");
                log("        multiple times.\n");
                log("\n");
+               log("    -map %%<design-name>\n");
+               log("        use the modules in this in-memory design as reference. This option can\n");
+               log("        be used multiple times.\n");
+               log("\n");
                log("    -verbose\n");
                log("        print debug output while analyzing\n");
                log("\n");
@@ -524,16 +528,32 @@ struct ExtractPass : public Pass {
                if (!mine_mode)
                {
                        map = new RTLIL::Design;
-                       for (auto &filename : map_filenames) {
-                               FILE *f = fopen(filename.c_str(), "rt");
-                               if (f == NULL)
-                                       log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
-                               Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
-                               fclose(f);
-
-                               if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
-                                       Pass::call(map, "proc");
-                                       Pass::call(map, "opt_clean");
+                       for (auto &filename : map_filenames)
+                       {
+                               if (filename.substr(0, 1) == "%")
+                               {
+                                       if (!saved_designs.count(filename.substr(1))) {
+                                               delete map;
+                                               log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
+                                       }
+                                       for (auto &it : saved_designs.at(filename.substr(1))->modules)
+                                               if (!map->modules.count(it.first))
+                                                       map->modules[it.first] = it.second->clone();
+                               }
+                               else
+                               {
+                                       FILE *f = fopen(filename.c_str(), "rt");
+                                       if (f == NULL) {
+                                               delete map;
+                                               log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
+                                       }
+                                       Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
+                                       fclose(f);
+
+                                       if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
+                                               Pass::call(map, "proc");
+                                               Pass::call(map, "opt_clean");
+                                       }
                                }
                        }
                }