back.pysim: Reuse clock simulation commands

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 398266e08aec128f30289353d4f3caebd464b364..f0fa2da99ec890ff328823fb81b8c4fd4e6a9a72 100644 (file)
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -1021,11 +1021,14 @@ class Simulator:
             # Behave correctly if the process is added after the clock signal is manipulated, or if
             # its reset state is high.
             initial = (yield domain.clk)
+            steps = (
+                domain.clk.eq(~initial),
+                Delay(half_period),
+                domain.clk.eq(initial),
+                Delay(half_period),
+            )
             while True:
-                yield domain.clk.eq(~initial)
-                yield Delay(half_period)
-                yield domain.clk.eq(initial)
-                yield Delay(half_period)
+                yield from iter(steps)
         self._add_coroutine_process(clk_process, default_cmd=None)
         self._clocked.add(domain)