radv: move shader stages calculation to pipeline.

With tess this becomes a bit more complex. so move to pipeline
for now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 04c28d6a29cb326c4469314686c21239c79584fe..e994df65fd2ce0b442ef05e3494f69838cf650ae 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1286,14 +1286,7 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
        }
 
        if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
-               uint32_t stages = 0;
-
-               if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
-                       stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
-                               S_028B54_GS_EN(1) |
-                               S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
-
-               radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
+               radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
 
                if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
                        radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 252808d7a7d7f491e2ffe18b4f9d1845f1fa8199..07020e8c387e69f1432ac538cb6b5d0da129d328 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1771,7 +1771,14 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 
        calculate_pa_cl_vs_out_cntl(pipeline);
        calculate_ps_inputs(pipeline);
-       
+
+       uint32_t stages = 0;
+       if (radv_pipeline_has_gs(pipeline))
+               stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
+                       S_028B54_GS_EN(1) |
+                       S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
+       pipeline->graphics.vgt_shader_stages_en = stages;
+
        const VkPipelineVertexInputStateCreateInfo *vi_info =
                pCreateInfo->pVertexInputState;
        for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 0b8c86df793e069365abedf6788896eb55a30b8b..f587ee3ffd84cf935511dc89aa4845b0cb108d41 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -965,6 +965,7 @@ struct radv_pipeline {
                        uint32_t ps_input_cntl[32];
                        uint32_t ps_input_cntl_num;
                        uint32_t pa_cl_vs_out_cntl;
+                       uint32_t vgt_shader_stages_en;
                        struct radv_prim_vertex_count prim_vertex_count;
                } graphics;
        };