BAD_PC_ADDRESSING condition.
testsuite/
* gas/arm/ldst-pc.d: New test.
* gas/arm/ldst-pc.s: New test.
* gas/arm/sp-pc-validations-bad.s: `str r0,[pc,#4]' is valid.
* gas/arm/sp-pc-validations-bad.l: Adjust accordingly.
+2010-08-25 Jie Zhang <jie@codesourcery.com>
+
+ * config/tc-arm.c (encode_arm_addr_mode_2): Fix
+ BAD_PC_ADDRESSING condition.
+
2010-08-20 Maciej W. Rozycki <macro@codesourcery.com>
* doc/c-arm.texi (ARM Options): Document -mfpu=fp4-sp-d16.
if (is_pc && !inst.reloc.pc_rel)
{
const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
- /* BAD_PC_ADDRESSING Condition =
- is_load => is_t
- which becomes !is_load || is_t. */
- constraint ((!is_load || is_t),
+
+ /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
+ cannot use PC in addressing.
+ PC cannot be used in writeback addressing, either. */
+ constraint ((is_t || inst.operands[i].writeback),
BAD_PC_ADDRESSING);
+
+ /* Use of PC in str is deprecated for ARMv7-A. */
+ if (warn_on_deprecated
+ && !is_load
+ && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
+ as_warn (_("use of PC in this instruction is deprecated"));
}
if (inst.reloc.type == BFD_RELOC_UNUSED)
+2010-08-25 Jie Zhang <jie@codesourcery.com>
+
+ * gas/arm/ldst-pc.d: New test.
+ * gas/arm/ldst-pc.s: New test.
+ * gas/arm/sp-pc-validations-bad.s: `str r0,[pc,#4]' is valid.
+ * gas/arm/sp-pc-validations-bad.l: Adjust accordingly.
+
2010-08-17 Roland McGrath <roland@redhat.com>
* gas/elf/groupauto.s: New file.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARM load/store with pc base register
+#as: -mno-warn-deprecated
+
+# Test the standard ARM instructions:
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> e51f1008 ldr r1, \[pc, #-8\] ; 0+000 <[^>]*>
+0+004 <[^>]*> e79f1002 ldr r1, \[pc, r2\]
+0+008 <[^>]*> f55ff008 pld \[pc, #-8\] ; 0+008 <[^>]*>
+0+00c <[^>]*> f7dff001 pld \[pc, r1\]
+0+010 <[^>]*> f45ff008 pli \[pc, #-8\] ; 0+010 <[^>]*>
+0+014 <[^>]*> f6dff001 pli \[pc, r1\]
+0+018 <[^>]*> e58f1004 str r1, \[pc, #4\] ; 0+024 <[^>]*>
--- /dev/null
+@ Test file for ARM load/store instructions with pc as the base register
+
+ .text
+ .syntax unified
+ .align 2
+ ldr r1, [pc, #-8]
+ ldr r1, [pc, r2]
+
+ pld [pc, #-8]
+ pld [pc, r1]
+
+ pli [pc, #-8]
+ pli [pc, r1]
+
+ str r1, [pc, #4]
[^:]*:158: Error: r15 not allowed here -- `ldrt pc,\[r0\],r1,LSL#4'
[^:]*:159: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],r1,LSL#4'
[^:]*:160: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[r1\],pc,LSL#4'
-[^:]*:165: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc,#4\]'
[^:]*:166: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc\],#4'
[^:]*:167: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc,#4\]!'
[^:]*:170: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1,pc,LSL#4\]'
ldrt r0,[pc],r1, LSL #4 @ ditto
ldrt r0,[r1],pc, LSL #4 @ ditto
+
@ Stores, ARM ================================================================
@ STR (immediate, ARM)
-str r0,[pc,#4] @ Unpredictable
-str r0,[pc],#4 @ ditto
+str r0,[pc],#4 @ Unpredictable
str r0,[pc,#4]! @ ditto
@ STR (register)