Fixed handling of transparent bram rd ports on ROMs

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ad90965fb583ba21b13ebadc8d6961c186e7120c..72809d42d6f9564b4e86fc00c91b938548773cab 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1482,6 +1482,7 @@ void RTLIL::Module::connect(const RTLIL::SigSig &conn)
                log_backtrace("-X- ", yosys_xtrace-1);
        }
 
+       log_assert(GetSize(conn.first) == GetSize(conn.second));
        connections_.push_back(conn);
 }
 

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 7b5dd08aba8b28af1506b6d228c2d66607235441..a7f9cf382d57cb51f729e9e5bc89631f6444c246 100644 (file)
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -656,6 +656,9 @@ grow_read_ports:;
                bool transp = rd_transp[cell_port_i] == State::S1;
                SigBit clksig = rd_clk[cell_port_i];
 
+               if (wr_ports == 0)
+                       transp = false;
+
                pair<SigBit, bool> clkdom(clksig, clkpol);
                if (!clken)
                        clkdom = pair<SigBit, bool>(State::S1, false);