c->prog_data.curb_read_length = reg - 1;
-
-
/* Allocate input regs:
*/
c->nr_inputs = 0;
c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0);
reg++;
}
- }
-
+ }
/* Allocate outputs: TODO: could organize the non-position outputs
* to go straight into message regs.
}
}
+
static void emit_math2( struct brw_vs_compile *c,
GLuint function,
struct brw_reg dst,
release_tmp(c, tmp);
}
}
-
static void emit_exp_noalias( struct brw_vs_compile *c,
}
-
-
/* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
*/
static void emit_dst_noalias( struct brw_vs_compile *c,
brw_MOV(p, brw_writemask(dst, WRITEMASK_W), arg1);
}
+
static void emit_xpd( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg t,
}
-
static void emit_lit_noalias( struct brw_vs_compile *c,
struct brw_reg dst,
struct brw_reg arg0 )
}
-
-
-
/* TODO: relative addressing!
*/
static struct brw_reg get_reg( struct brw_vs_compile *c,
}
-
static struct brw_reg deref( struct brw_vs_compile *c,
struct brw_reg arg,
GLint offset)
}
-
-
static void emit_swz( struct brw_vs_compile *c,
struct brw_reg dst,
struct prog_src_register src )
}
-
-/* Post-vertex-program processing. Send the results to the URB.
+/**
+ * Post-vertex-program processing. Send the results to the URB.
*/
static void emit_vertex_write( struct brw_vs_compile *c)
{
get_reg(c, PROGRAM_INPUT, VERT_ATTRIB_EDGEFLAG));
}
-
/* Build ndc coords */
if (!c->key.know_w_is_one) {
ndc = get_tmp(c);
brw_AND(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(0x7ff<<8));
}
-
for (i = 0; i < c->key.nr_userclip; i++) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_L);
brw_DP4(p, brw_null_reg(), pos, c->userplane[i]);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
-
/* i965 clipping workaround:
* 1) Test for -ve rhw
* 2) If set,
brw_MOV(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD), brw_imm_ud(0));
}
-
/* Emit the (interleaved) headers for the two vertices - an 8-reg
* of zeros followed by two sets of NDC coordinates:
*/
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, offset(m0, 2), ndc);
brw_MOV(p, offset(m0, 3), pos);
-
brw_urb_WRITE(p,
brw_null_reg(), /* dest */
1, /* writes complete */
0, /* urb destination offset */
BRW_URB_SWIZZLE_INTERLEAVE);
-
}
+
static void
post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst )
{
break;
case OPCODE_SGT:
emit_sgt(p, dst, args[0], args[1]);
- break;
+ break;
case OPCODE_SLT:
emit_slt(p, dst, args[0], args[1]);
break;
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
brw_set_predicate_control_flag_value(p, 0xff);
- break;
+ break;
case OPCODE_CAL:
brw_set_access_mode(p, BRW_ALIGN_1);
brw_ADD(p, deref_1d(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
get_addr_reg(stack_index), brw_imm_d(4));
inst->Data = &p->store[p->nr_insn];
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
- break;
+ break;
case OPCODE_RET:
brw_ADD(p, get_addr_reg(stack_index),
get_addr_reg(stack_index), brw_imm_d(-4));
brw_set_access_mode(p, BRW_ALIGN_16);
case OPCODE_END:
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
- break;
+ break;
case OPCODE_PRINT:
case OPCODE_BGNSUB:
case OPCODE_ENDSUB:
+ /* no-op instructions */
break;
default:
_mesa_printf("Unsupported opcode %i (%s) in vertex shader\n",