add biginteger analysis chapter

diff --git a/openpower/Makefile b/openpower/Makefile
index 677684dc8c6bf2661f5add037e7c8816bc7864cb..b85af2e2ed5c6ba71643ee1742a5df2e4dc8d77a 100755 (executable)
--- a/openpower/Makefile
+++ b/openpower/Makefile
@@ -78,6 +78,12 @@ tex:
        pandoc -f markdown -t latex --top-level-division=section \
                --filter pandoc_img.py \
                        -N -o tex_out/av_opcodes.tex sv/av_opcodes.mdwn
+       pandoc -f markdown -t latex --top-level-division=section \
+               --filter pandoc_img.py \
+                       -N -o tex_out/big_integer.tex sv/biginteger.mdwn
+       pandoc -f markdown -t latex --top-level-division=section \
+               --filter pandoc_img.py \
+                       -N -o tex_out/big_integer_analysis.tex sv/biginteger/analysis.mdwn
 
 
 pdf:

diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex
index a31dbb7b974e1be41bbf81cd45d2f8e8664d0ae1..0012227c9adc96cdb3e93ea2b22d39c75527e789 100644 (file)
--- a/openpower/simple_v_spec.tex
+++ b/openpower/simple_v_spec.tex
@@ -200,6 +200,10 @@ Programme, requires full transparency.
 \input{tex_out/int_fp_mv.tex}
 \chapter{Audio/Video ops}\hypertarget{svux2fav_opcodes}{}
 \input{tex_out/av_opcodes.tex}
+\chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
+\input{tex_out/big_integer.tex}
+\chapter{Big Integer}\hypertarget{svux2fbigintegerux2fanalysis}{}
+\input{tex_out/big_integer_analysis.tex}
 
 
 

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index fa14bc4d3354295cf32d00cb82d5c98964fd3f93..3b13a59401cd19dc9590888d84eb0a351269529e 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -168,15 +168,18 @@ Stand-alone Scalar Instructions:
 * [[sv/fclass]] detect class of FP numbers
 * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
-* Twin targetted instructions (two registers out, one implicit, just like
-  Load-with-Update).
-  Explanation of the rules for twin register targets
-  (implicit RS, FRS) explained in SVP64 [[svp64/appendix]]
-  - [[isa/svfixedarith]]
-  - [[isa/svfparith]]
-  - [[sv/biginteger]] Operations that help with big arithmetic
 * TODO: OpenPOWER adaptation [[openpower/transcendentals]]
 
+Twin targetted instructions (two registers out, one implicit, just like
+Load-with-Update).
+
+* [[isa/svfixedarith]]
+* [[isa/svfparith]]
+* [[sv/biginteger]] Operations that help with big arithmetic
+
+Explanation of the rules for twin register targets
+(implicit RS, FRS) explained in SVP64 [[svp64/appendix]]
+
 # Other Scalable Vector ISAs
 
 These Scalable Vector ISAs are listed to aid in understanding and